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1.发明授权公开(公告)号：US10439850B2
公开(公告)日：2019-10-08
申请号：US15660723
申请日：2017-07-26
Applicant: MOTOROLA SOLUTIONS, INC.
Inventor： Joseph P. Heck , Christopher Calvo , Rodger W. Caruthers , Nicholas G. Cafaro , Geetha B. Nagaraj , Raul Salvi
Abstract: Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system includes a first receive path configured to directly sample a first signal in a first frequency range. The system includes a second receive path configured to convert a second signal in a second frequency range. The second receive path includes a receive modulator operating over a duty cycle. The receive modulator is configured to adjust the duty cycle by a predetermined scaling factor.
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2.发明授权Systems and methods for generating injection-locked, frequency-multiplied output signals 有权用于产生注入锁定，倍频输出信号的系统和方法公开(公告)号：US09564880B2
公开(公告)日：2017-02-07
申请号：US14581337
申请日：2014-12-23
Applicant: MOTOROLA SOLUTIONS, INC.
Inventor： Robert E. Stengel , Nicholas G. Cafaro
CPC classification number: H03K3/0315 , H03K5/00006
Abstract: Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).
Abstract translation: 这里公开了用于产生注入锁定倍频输出信号的系统和方法。 在一个实施例中，电路包括数个（N）个串行连接的延迟缓冲元件的环和一个注入脉冲发生电路。 每个延迟缓冲元件提供时间延迟（D），并且它们中的至少一些具有至少一个脉冲锁定注入端口。 注入脉冲发生电路被配置为发送平衡延迟注入脉冲信号，其通过将平衡延迟选择逻辑根据脉冲选择控制信号施加到时钟信号而产生到脉冲锁定注入端口，以提供 在环形输出端口处，具有等于（N * D）的倒数的频率的注入锁定倍频输出信号，并且与时钟信号的频率成比例关系，时钟周期的周期 信号为（N * D）。
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公开(公告)号：US11387859B2
公开(公告)日：2022-07-12
申请号：US16915041
申请日：2020-06-29
Applicant: MOTOROLA SOLUTIONS, INC.
Inventor： Sumit A Talwalkar , Geetha B. Nagaraj , Nicholas G. Cafaro
Abstract: An improved superheterodyne receiver for a portable radio is provided. The receiver includes a frequency controller that applies pulse-shaped modulation to first and second LO signals in a synchronized manner. The frequency controller is steered by Artificial Intelligence (AI) based machine learning (ML) to determine first and second LOs that minimize image interference in the baseband signal.
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4.发明申请公开(公告)号：US20190036747A1
公开(公告)日：2019-01-31
申请号：US15660723
申请日：2017-07-26
Applicant: MOTOROLA SOLUTIONS, INC.
Inventor： Joseph P. Heck , Christopher Calvo , Rodger W. Caruthers , Nicholas G. Cafaro , Geetha B. Nagaraj , Raul Salvi
CPC classification number: H04L27/14 , H03K5/1565 , H04B1/0007 , H04B1/16
Abstract: Systems and methods for processing radiofrequency signals using modulation duty cycle scaling. One system includes a first receive path configured to directly sample a first signal in a first frequency range. The system includes a second receive path configured to convert a second signal in a second frequency range. The second receive path includes a receive modulator operating over a duty cycle. The receive modulator is configured to adjust the duty cycle by a predetermined scaling factor.
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