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1.发明授权Method and apparatus for single port modulation using a fractional-N modulator 有权使用分数N调制器进行单端口调制的方法和装置公开(公告)号：US09035682B2
公开(公告)日：2015-05-19
申请号：US13730932
申请日：2012-12-29
CPC分类号： H03L7/1974 , H03C3/0925 , H03C3/0933 , H03L7/235
摘要： A method and apparatus for single port modulation of a phase locked loop frequency modulator includes a phase locked loop with a voltage controlled oscillator (VCO) and a integer loop for multiplying up the output of the VCO which is divided by a fractional-N modulator and divider in the feedback control. The integer loop enables the use of a high frequency reference oscillator that allows a closed loop response of the phase locked loop having a bandwidth that is wider than the modulation bandwidth.
摘要翻译： 用于锁相环频率调制器的单端口调制的方法和装置包括具有压控振荡器（VCO）的锁相环和用于将由分数N调制器分频的VCO的输出相乘的整数循环和 分频器在反馈控制中。 整数循环使得能够使用高频参考振荡器，其允许具有比调制带宽宽的带宽的锁相环的闭环响应。
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2.发明授权Systems and methods for generating injection-locked, frequency-multiplied output signals 有权用于产生注入锁定，倍频输出信号的系统和方法公开(公告)号：US09564880B2
公开(公告)日：2017-02-07
申请号：US14581337
申请日：2014-12-23
CPC分类号： H03K3/0315 , H03K5/00006
摘要： Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).
摘要翻译： 这里公开了用于产生注入锁定倍频输出信号的系统和方法。 在一个实施例中，电路包括数个（N）个串行连接的延迟缓冲元件的环和一个注入脉冲发生电路。 每个延迟缓冲元件提供时间延迟（D），并且它们中的至少一些具有至少一个脉冲锁定注入端口。 注入脉冲发生电路被配置为发送平衡延迟注入脉冲信号，其通过将平衡延迟选择逻辑根据脉冲选择控制信号施加到时钟信号而产生到脉冲锁定注入端口，以提供 在环形输出端口处，具有等于（N * D）的倒数的频率的注入锁定倍频输出信号，并且与时钟信号的频率成比例关系，时钟周期的周期 信号为（N * D）。
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