公开(公告)号：US08949764B2

公开(公告)日：2015-02-03

申请号：US13479807

申请日：2012-05-24

申请人： Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively.

摘要翻译： 描述排除库单元的方法和系统。 一些实施例为库单元类型的定时弧接收通用逻辑努力值和可选的通用寄生延迟值。 接下来，排除库单元类型的库单元，其定时弧的特定逻辑努力值大于通用逻辑努力值大于第一阈值和/或可选地其定时弧的特定寄生延迟值大于 通用寄生延迟值大于第二阈值。 可以基于至少一些剩余的库单元来确定新的通用逻辑努力值和可选的新的通用寄生延迟值。 可以迭代地执行排除库单元和确定新的通用逻辑努力值以及可选的新的通用寄生延迟值的过程。

公开(公告)号：US20140007037A1

公开(公告)日：2014-01-02

申请号：US13537880

申请日：2012-06-29

申请人： Amir H. Mottaez ,  Mahesh A. Iyer

发明人： Amir H. Mottaez ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068

摘要： Systems and techniques are described for estimating optimal gate sizes in a circuit design using numerical delay models of cells and cell types in a technology library. Gate sizes are optimized in the circuit design in a reverse-levelized processing order. Gates that are at the same level in the reverse-levelized processing order, and whose inputs are electrically connected to the same driver output are optimized together. A closed-form expression is used to determine the optimized size for each gate in a set of gates that are optimized together. Some embodiments perform multiple optimization iterations, wherein in each optimization iteration all of the gates in the circuit design are processed in the reverse-levelized processing order. The iterative optimization process terminates when one or more termination conditions are met.

摘要翻译： 描述了使用技术库中的单元和单元类型的数值延迟模型来估计电路设计中的最佳栅极尺寸的系统和技术。 栅极尺寸在电路设计中以反向级别化处理顺序进行了优化。 处于相反级别的处理顺序处于相同级别的门并且其输入电连接到相同的驱动器输出的门优化在一起。 闭合表达式用于确定一组优化的一组门中每个门的优化大小。 一些实施例执行多个优化迭代，其中在每个优化迭代中，电路设计中的所有门都以反向均衡的处理顺序被处理。 当满足一个或多个终止条件时，迭代优化过程终止。

公开(公告)号：US20130283222A1

公开(公告)日：2013-10-24

申请号：US13450178

申请日：2012-04-18

申请人： Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.

摘要翻译： 描述了基于一个或多个离散延迟模型确定数值延迟模型的方法和系统。 离散延迟模型是一种延迟模型，其中使用延迟行为的一组离散数据点表示延迟行为。 数值延迟模型是可以由数值求解器用于优化成本函数的延迟模型。 一般来说，使用数字延迟模型的计算延迟明显快于使用离散延迟模型的计算延迟。 由于在电路优化方法中需要重复的延迟计算，因此在优化诸如定时，面积和漏电功率等各种度量标准的设计时，这种性能改进非常重要。

公开(公告)号：US08762905B2

公开(公告)日：2014-06-24

申请号：US13450178

申请日：2012-04-18

申请人： Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.

摘要翻译： 描述了基于一个或多个离散延迟模型确定数值延迟模型的方法和系统。 离散延迟模型是一种延迟模型，其中使用延迟行为的一组离散数据点表示延迟行为。 数值延迟模型是可以由数值求解器用于优化成本函数的延迟模型。 一般来说，使用数字延迟模型的计算延迟明显快于使用离散延迟模型的计算延迟。 由于在电路优化方法中需要重复的延迟计算，因此在优化诸如定时，面积和漏电功率等各种度量标准的设计时，这种性能改进非常重要。

公开(公告)号：US20140040851A1

公开(公告)日：2014-02-06

申请号：US13563316

申请日：2012-07-31

申请人： Amir H. Mottaez ,  Mahesh A. Iyer

发明人： Amir H. Mottaez ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/505 ,  G06F2217/84

摘要： Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations.

摘要翻译： 描述了用于优化电路设计的系统和技术。 具体来说，通过迭代地执行一组操作来优化电路设计中的栅极尺寸，该组操作包括但不限于：选择电路设计的一部分（例如，根据反向级别的处理顺序），选择输入 - 在电路设计的部分中驱动器门的输出电弧，在电路设计的部分中选择栅极以进行优化，基于所选择的驱动器门的输入到输出电弧对所选择的栅极优化问题进行建模，并且所选择的 门，解决门优化问题，以获得使用一个或多个求解器的解决方案，并离散化解决方案。 离散化解决方案涉及识别与解决方案中指定的栅极大小完全匹配或匹配的库单元格。 然后可以使用这些库单元来模拟当前或后续迭代中的其他门优化问题。

公开(公告)号：US20140033162A1

公开(公告)日：2014-01-30

申请号：US13562189

申请日：2012-07-30

申请人： Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver.

摘要翻译： 描述了通过使用数值求解器优化电路设计的系统和技术。 门尺寸通过对一组门优化问题建模进行优化，并通过使用数值求解器来求解一组门优化问题。 对每个栅极优化问题进行建模可以包括选择电路设计的一部分，该部分包括驱动器门，该驱动器栅极驱动一组栅极中的每个栅极的一个或多个输入，以及基于电路为电路设计的部分建模栅极优化问题 信息部分的电路设计。 可以使用用于电路中的延迟的数值模型来创建用于延迟的可微分目标函数。 在一些实施例中，可计算可微分目标函数的梯度以使得能够使用基于共轭梯度的数值求解器。

公开(公告)号：US20130326449A1

公开(公告)日：2013-12-05

申请号：US13485600

申请日：2012-05-31

申请人： Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

摘要： Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the set of delays corresponds to a delay between the driver pin and a corresponding load pin in the set of load pins. As load pin capacitances change during circuit optimization, the set of incremental Elmore delay coefficients can then be used to update the delays between the driver pin and the load pins in a very computationally efficient manner.

摘要翻译： 描述了用于递增更新Elmore引脚到引脚延迟的系统和技术。 在操作期间，实施例接收将驱动器引脚电连接到一组负载引脚的布线网的物理拓扑的表示。 然后，该实施例基于该表示来计算一组增量Elmore延迟系数。 接下来，使用Elmore延迟系数，该实施例基于该表示计算一组延迟，其中延迟组中的每个延迟对应于驱动器引脚和该组负载引脚中的相应负载引脚之间的延迟。 由于负载引脚电容在电路优化期间发生变化，所以增量Elmore延迟系数组可用于以非常计算效率的方式更新驱动器引脚和负载引脚之间的延迟。

公开(公告)号：US20110191740A1

公开(公告)日：2011-08-04

申请号：US12697168

申请日：2010-01-29

申请人： Robert Walker ,  Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Robert Walker ,  Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5081

摘要： Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.

摘要翻译： 本发明的一些实施例提供用于有效地优化一个或多个多模式多角（MCMM）场景的电路设计的技术和系统。 系统可以选择用于逻辑门的优化变换，其如果应用于逻辑门，则不降低逻辑门的本地上下文中的定时度量。 接下来，系统可以确定将优化变换应用于逻辑门是否会降低逻辑门周围区域中的定时度量。 如果是这样，系统可以拒绝优化转换。 否则，系统可以确定将优化变换应用于逻辑门是否会降低电路设计中的定时度量。 如果是这样，系统可以拒绝优化转换。 否则，系统可以接受优化转换。

公开(公告)号：US09384309B2

公开(公告)日：2016-07-05

申请号：US12783915

申请日：2010-05-20

申请人： Mahesh A. Iyer ,  Amir H. Mottaez ,  Rajnish K. Prasad

发明人： Mahesh A. Iyer ,  Amir H. Mottaez ,  Rajnish K. Prasad

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045 ,  G06F17/505 ,  G06F2217/08 ,  G06F2217/84

摘要： Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.

摘要翻译： 本发明的一些实施例提供了用于确定和使用边缘值的技术和系统。 可以确定逻辑门的输出引脚的到达时间。 接下来，可以确定逻辑门的输出引脚所需的时间。 每个所需的时间可以与路径组中的定时终点相关联，受该引脚的影响。 然后，系统可以通过计算所需时间和到达时间之间的差异来确定逻辑门的输出引脚处的第一组松弛值。 接下来，系统可以通过计算在路径组中的定时终点处的第一组松弛值和第二组松弛值之间的差来确定逻辑门的输出引脚处的一组余量值。 接下来，系统可以使用一组余量值来优化逻辑门。

公开(公告)号：US20130318488A1

公开(公告)日：2013-11-28

申请号：US13479807

申请日：2012-05-24

申请人： Mahesh A. Iyer ,  Amir H. Mottaez

发明人： Mahesh A. Iyer ,  Amir H. Mottaez

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively.

摘要翻译： 描述排除库单元的方法和系统。 一些实施例为库单元类型的定时弧接收通用逻辑努力值和可选的通用寄生延迟值。 接下来，排除库单元类型的库单元，其定时弧的特定逻辑努力值大于通用逻辑努力值大于第一阈值和/或可选地其定时弧的特定寄生延迟值大于 通用寄生延迟值大于第二阈值。 可以基于至少一些剩余的库单元来确定新的通用逻辑努力值和可选的新的通用寄生延迟值。 可以迭代地执行排除库单元和确定新的通用逻辑努力值以及可选的新的通用寄生延迟值的过程。