公开(公告)号：US06576854B2

公开(公告)日：2003-06-10

申请号：US09968825

申请日：2001-10-02

申请人： Makoto Yamanaka ,  Yutaka Sekino

发明人： Makoto Yamanaka ,  Yutaka Sekino

IPC分类号： H01H902

CPC分类号： H01H13/06 ,  E05B81/76 ,  H01H2009/048

摘要： The invention provides a waterproof switch which can electrically open and close an door of a vehicle body by a switch, can achieve a seal between a waterproof switch and a panel and a seal against an inner portion of the waterproof switch by one seal member, and previously make a seal member hold in a side of the waterproof switch at a time of assembling. The waterproof switch comprises: a base (1) having a seal surface (17); a push rod (3) moving against an urging force so as to open or close a contact point; a seal member (5) having a head cover portion (31), a panel seal portion (33) and a base seal portion (35); and a case (7) provided with a mounting and engaging portion (37), and a seal assist portion (39) pressing the base seal portion (35) to the seal surface (17) of the base (1) in a mounting state of the mounting and engaging portion (37) and closely attaching the panel seal portion (33) to a panel (OP) at a time of supporting the panel seal portion (33) so as to mount the base (1) to a side of the panel (OP).

公开(公告)号：US08503259B2

公开(公告)日：2013-08-06

申请号：US12382485

申请日：2009-03-17

申请人： Shogo Shibazaki ,  Shinkichi Gama ,  Hideyuki Negi ,  Takeshi Nagase ,  Chikahiro Deguchi ,  Yutaka Sekino

发明人： Shogo Shibazaki ,  Shinkichi Gama ,  Hideyuki Negi ,  Takeshi Nagase ,  Chikahiro Deguchi ,  Yutaka Sekino

IPC分类号： G11C29/00

CPC分类号： G11C29/20 ,  G11C2029/3602

摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.

摘要翻译： 通过顺序地生成多个n位地址来执行存储器测试，其中第一到第k位（1 @ k @ n）都被设置为两个值0或1中的一个，并且其（k + 1） 对于从1到n的所有k，所有第th到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

公开(公告)号：US08143901B2

公开(公告)日：2012-03-27

申请号：US12379371

申请日：2009-02-19

申请人： Chikahiro Deguchi ,  Yutaka Sekino ,  Shogo Shibazaki ,  Shinkichi Gama ,  Takeshi Nagase ,  Hideyuki Negi

发明人： Chikahiro Deguchi ,  Yutaka Sekino ,  Shogo Shibazaki ,  Shinkichi Gama ,  Takeshi Nagase ,  Hideyuki Negi

IPC分类号： G01R31/02

CPC分类号： G11C29/20 ,  G11C29/56004 ,  G11C2029/3602

摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.

摘要翻译： 测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或 由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

公开(公告)号：US20090300443A1

公开(公告)日：2009-12-03

申请号：US12379371

申请日：2009-02-19

申请人： Chikahiro Deguchi ,  Yutaka Sekino ,  Shogo Shibazaki ,  Shinkichi Gama ,  Takeshi Nagase ,  Hideyuki Negi

发明人： Chikahiro Deguchi ,  Yutaka Sekino ,  Shogo Shibazaki ,  Shinkichi Gama ,  Takeshi Nagase ,  Hideyuki Negi

IPC分类号： G06F11/22

CPC分类号： G11C29/20 ,  G11C29/56004 ,  G11C2029/3602

摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.

摘要翻译： 测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或 由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

公开(公告)号：US20050284736A1

公开(公告)日：2005-12-29

申请号：US11165785

申请日：2005-06-23

申请人： Yutaka Sekino ,  Hideji Onodera ,  Takeshi Fujimoto

发明人： Yutaka Sekino ,  Hideji Onodera ,  Takeshi Fujimoto

IPC分类号： H01H25/04 ,  H01H13/72

CPC分类号： H01H25/041 ,  H01H2025/046 ,  H01H2221/058 ,  H01H2300/012

摘要： In a switch device including: a push button disposed in an opening of a switch case and operable to be tilted in any one of a plurality of directions by being pushed at an outer edge side; a rubber contact that forces the push button to a position before pushing; and a movable contact and a fixed contact connectable to each other by each pushing operation on the push button, a convex portion and a concave portion that can be spaced apart from each other are separately provided to the push button and the switch case for rotational support and positional regulation of the push button with respect to the switch case at the time of a tilting operation by each pushing.

摘要翻译： 一种开关装置，包括：按钮，设置在开关壳体的开口中，并且可操作以通过在外边缘侧被推动而在多个方向中的任一个上倾斜; 一个橡胶触点，迫使按钮推到一个位置; 以及通过按钮上的每个按压操作而可连接的可动触点和固定触点，能够彼此间隔开的凸部和凹部分别设置在按钮和用于旋转支撑的开关壳体 以及通过每次按压在倾斜操作时相对于开关壳体的按钮的位置调节。

公开(公告)号：US6111326A

公开(公告)日：2000-08-29

申请号：US52925

申请日：1998-04-01

申请人： Yukio Miyata ,  Yutaka Sekino ,  Shigeru Hatakeyama ,  Atsushi Sakagami

发明人： Yukio Miyata ,  Yutaka Sekino ,  Shigeru Hatakeyama ,  Atsushi Sakagami

IPC分类号： B60R16/02 ,  B60R16/037 ,  E05F15/16 ,  H02P1/22

CPC分类号： B60R16/037 ,  E05F15/689 ,  E05Y2900/55

摘要： There is provided a control circuit which can perform a control of opening and closing an opening/closing device, a sun roof in a vehicle, or the like. Usually, an I UP direction current is supplied to a motor 9 according to an ON-operation by an UP switch 3, and an I DOWN direction current is supplied to a motor 9 according to an ON-operation by a DOWN switch 5. If any failures occur, even if the I UP direction current is supplied to the motor 9 when the UP switch 3 is not on-operated, in accordance with the ON-operation of the DOWN switch 5, the current is switched over to the I DOWN direction, and then, is supplied to the motor 9.

摘要翻译： 提供了一种能够执行打开和关闭打开/关闭装置，车辆中的太阳屋顶等的控制的控制电路。 通常，根据UP开关3的接通操作，向电动机9提供I UP方向电流，并且通过DOWN开关5根据ON操作向电动机9提供I DOWN方向电流。如果 任何故障都会发生，即使当UP开关3未接通操作时I UP方向电流被提供给电动机9时，根据DOWN开关5的接通操作，电流被切换到I DOWN 方向，然后被提供给电动机9。

公开(公告)号：US07880102B2

公开(公告)日：2011-02-01

申请号：US11773702

申请日：2007-07-05

申请人： Takahiko Mitsui ,  Yutaka Sekino

发明人： Takahiko Mitsui ,  Yutaka Sekino

IPC分类号： H01H9/00

CPC分类号： B60Q1/1469

摘要： An attachment structure includes a bracket that is arranged around a steering, a rotary connector device that has an engagement portion for being provisionally fixed to the bracket in a provisionally fixed state, and a combination switch that has a guide portion for being slidably retained to the bracket in the provisionally fixed state. The rotary connector device and the combination switch are completely fastened together with the bracket by a screw member from the provisionally fixed state.

摘要翻译： 附接结构包括：设置在转向盘周围的支架;旋转连接器装置，其具有用于临时固定在支架上的接合部分，并具有临时固定状态的组合开关;以及组合开关， 支架处于临时固定状态。 旋转连接器装置和组合开关通过螺钉构件与支架完全紧固在一起，处于临时固定状态。

公开(公告)号：US20090296505A1

公开(公告)日：2009-12-03

申请号：US12382485

申请日：2009-03-17

申请人： Shogo Shibazaki ,  Shinkichi Gama ,  Hideyuki Negi ,  Takeshi Nagase ,  Chikahiro Deguchi ,  Yutaka Sekino

发明人： Shogo Shibazaki ,  Shinkichi Gama ,  Hideyuki Negi ,  Takeshi Nagase ,  Chikahiro Deguchi ,  Yutaka Sekino

IPC分类号： G11C29/00

CPC分类号： G11C29/20 ,  G11C2029/3602

摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.

摘要翻译： 通过顺序地生成多个n位地址来执行存储器测试，其中第一至第k位（1 <= k <= n）都被设置为两个值0或1之一，并且其（k + 对于从1到n的所有k，所有1到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

公开(公告)号：US07180018B2

公开(公告)日：2007-02-20

申请号：US11165785

申请日：2005-06-23

申请人： Yutaka Sekino ,  Hideji Onodera ,  Takeshi Fujimoto

发明人： Yutaka Sekino ,  Hideji Onodera ,  Takeshi Fujimoto

IPC分类号： H01H9/26 ,  H01H13/72 ,  H01H13/76

CPC分类号： H01H25/041 ,  H01H2025/046 ,  H01H2221/058 ,  H01H2300/012

摘要： In a switch device including: a push button disposed in an opening of a switch case and operable to be tilted in any one of a plurality of directions by being pushed at an outer edge side; a rubber contact that forces the push button to a position before pushing; and a movable contact and a fixed contact connectable to each other by each pushing operation on the push button, a convex portion and a concave portion that can be spaced apart from each other are separately provided to the push button and the switch case for rotational support and positional regulation of the push button with respect to the switch case at the time of a tilting operation by each pushing.

摘要翻译： 一种开关装置，包括：按钮，设置在开关壳体的开口中，并且可操作以通过在外边缘侧被推动而在多个方向中的任一个上倾斜; 一个橡胶触点，迫使按钮推到一个位置; 以及通过按钮上的每个按压操作而可连接的可动触点和固定触点，能够彼此间隔开的凸部和凹部分别设置在按钮和用于旋转支撑的开关壳体 以及通过每次按压在倾斜操作时相对于开关壳体的按钮的位置调节。

公开(公告)号：US07096406B2

公开(公告)日：2006-08-22

申请号：US10097499

申请日：2002-03-15

申请人： Keisuke Kanazawa ,  Hiroaki Watanabe ,  Yoshinobu Higuchi ,  Hideki Arakawa ,  Yoshiki Okumura ,  Yutaka Sekino

发明人： Keisuke Kanazawa ,  Hiroaki Watanabe ,  Yoshinobu Higuchi ,  Hideki Arakawa ,  Yoshiki Okumura ,  Yutaka Sekino

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G06F11/1072 ,  G11C11/5621

摘要： A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is no redundancy in the n bits of data associated with one N-level cell. Together with this, the memory controller separates the plurality of data bits on the first data bus into first through Mth data groups, the ECC circuits generate error-correction codes for each of these data groups, and the first through Mth data groups and first through Mth error correction codes are input to the first through Mth data input/output terminals of the N-level cell memory, via the second data bus.