Assigning tasks to processors in heterogeneous multiprocessors
    1.
    发明授权
    Assigning tasks to processors in heterogeneous multiprocessors 有权
    将任务分配给异构多处理器中的处理器

    公开(公告)号:US08230425B2

    公开(公告)日:2012-07-24

    申请号:US11830588

    申请日:2007-07-30

    CPC分类号: G06F9/5044

    摘要: Methods and arrangements of assigning tasks to processors are discussed. Embodiments include transformations, code, state machines or other logic to detect an attempt to execute an instruction of a task on a processor not supporting the instruction (non-supporting processor). The method may involve selecting a processor supporting the instruction (supporting physical processor). In many embodiments, the method may include storing data about the attempt to execute the instruction and, based upon the data, making another assignment of the task to a physical processor supporting the instruction. In some embodiments, the method may include representing the instruction set of a virtual processor as the union of the instruction sets of the physical processors comprising the virtual processor and assigning a task to the virtual processor based upon the representing.

    摘要翻译: 讨论了将任务分配给处理器的方法和布置。 实施例包括转换,代码,状态机或用于检测在不支持指令(非支持处理器)的处理器上执行任务的指令的其他逻辑。 该方法可以涉及选择支持指令(支持物理处理器)的处理器。 在许多实施例中,该方法可以包括存储关于执行该指令的尝试的数据,并且基于该数据,将该任务的另一个分配给支持该指令的物理处理器。 在一些实施例中,该方法可以包括将虚拟处理器的指令集表示为包括虚拟处理器的物理处理器的指令集的并集,并且基于该表示将任务分配给虚拟处理器。

    ASSIGNING TASKS TO PROCESSORS IN HETEROGENEOUS MULTIPROCESSORS
    2.
    发明申请
    ASSIGNING TASKS TO PROCESSORS IN HETEROGENEOUS MULTIPROCESSORS 有权
    将任务分配给异构多处理器中的处理器

    公开(公告)号:US20090037911A1

    公开(公告)日:2009-02-05

    申请号:US11830588

    申请日:2007-07-30

    IPC分类号: G06F9/46

    CPC分类号: G06F9/5044

    摘要: Methods and arrangements of assigning tasks to processors are discussed. Embodiments include transformations, code, state machines or other logic to detect an attempt to execute an instruction of a task on a processor not supporting the instruction (non-supporting processor). The method may involve selecting a processor supporting the instruction (supporting physical processor). In many embodiments, the method may include storing data about the attempt to execute the instruction and, based upon the data, making another assignment of the task to a physical processor supporting the instruction. In some embodiments, the method may include representing the instruction set of a virtual processor as the union of the instruction sets of the physical processors comprising the virtual processor and assigning a task to the virtual processor based upon the representing.

    摘要翻译: 讨论了将任务分配给处理器的方法和布置。 实施例包括转换,代码,状态机或用于检测在不支持指令(非支持处理器)的处理器上执行任务的指令的其他逻辑。 该方法可以涉及选择支持指令(支持物理处理器)的处理器。 在许多实施例中,该方法可以包括存储关于执行该指令的尝试的数据,并且基于该数据,将该任务的另一个分配给支持该指令的物理处理器。 在一些实施例中,该方法可以包括将虚拟处理器的指令集表示为包括虚拟处理器的物理处理器的指令集的并集,并且基于该表示将任务分配给虚拟处理器。

    Compiler optimized function variants for use when return codes are ignored
    3.
    发明授权
    Compiler optimized function variants for use when return codes are ignored 失效
    编译器优化的函数变体,当忽略返回代码时使用

    公开(公告)号:US08291397B2

    公开(公告)日:2012-10-16

    申请号:US12060894

    申请日:2008-04-02

    IPC分类号: G06F9/45

    CPC分类号: G06F8/49

    摘要: A mechanism and functionality are provided for generating and using compiler optimized function variants. These variants may be used, for example, in situations where return values of functions called by code are not thereafter used by the code calling the functions. In particular, for a function called by computer code, at least two variants for the function may be generated. A function call, for calling the function, within original computer code may be analyzed to determine which variant of the at least two variants to use for the function call. The function call may be modified in the original computer code, to generate modified computer code, based on results of the analysis identifying which variant of the at least two variants to use for the function call.

    摘要翻译: 提供了一种机制和功能,用于生成和使用编译器优化的功能变体。 这些变体可以用于例如在由代码调用的函数的返回值此后不被调用函数的代码使用的情况下。 特别地,对于由计算机代码调用的功能,可以生成用于该功能的至少两个变体。 可以分析用于在原始计算机代码内调用功能的函数调用,以确定用于函数调用的至少两个变体的哪个变体。 可以在原始计算机代码中修改函数调用,以基于分析结果识别用于函数调用的至少两个变体的哪个变体来生成修改的计算机代码。

    COMPILER OPTIMIZED FUNCTION VARIANTS FOR USE WHEN RETURN CODES ARE IGNORED
    4.
    发明申请
    COMPILER OPTIMIZED FUNCTION VARIANTS FOR USE WHEN RETURN CODES ARE IGNORED 失效
    当返回代码被忽略时使用的编译器优化函数变量

    公开(公告)号:US20090254893A1

    公开(公告)日:2009-10-08

    申请号:US12060894

    申请日:2008-04-02

    IPC分类号: G06F9/45

    CPC分类号: G06F8/49

    摘要: A mechanism and functionality are provided for generating and using compiler optimized function variants. These variants may be used, for example, in situations where return values of functions called by code are not thereafter used by the code calling the functions. In particular, for a function called by computer code, at least two variants for the function may be generated. A function call, for calling the function, within original computer code may be analyzed to determine which variant of the at least two variants to use for the function call. The function call may be modified in the original computer code, to generate modified computer code, based on results of the analysis identifying which variant of the at least two variants to use for the function call.

    摘要翻译: 提供了一种机制和功能,用于生成和使用编译器优化的功能变体。 这些变体可以用于例如在由代码调用的函数的返回值此后不被调用函数的代码使用的情况下。 特别地,对于由计算机代码调用的功能,可以生成用于该功能的至少两个变体。 可以分析用于在原始计算机代码内调用功能的函数调用,以确定用于函数调用的至少两个变体的哪个变体。 可以在原始计算机代码中修改函数调用,以基于分析结果识别用于函数调用的至少两个变体的哪个变体来生成修改的计算机代码。

    Dynamic Logical Partition Management For NUMA Machines And Clusters
    5.
    发明申请
    Dynamic Logical Partition Management For NUMA Machines And Clusters 有权
    NUMA机器和集群的动态逻辑分区管理

    公开(公告)号:US20100217949A1

    公开(公告)日:2010-08-26

    申请号:US12391827

    申请日:2009-02-24

    IPC分类号: G06F12/02

    CPC分类号: G06F9/5077

    摘要: A partitioned NUMA machine is managed to dynamically transform its partition layout state based on NUMA considerations. The NUMA machine includes two or more NUMA nodes that are operatively interconnected by one or more internodal communication links. Each node includes one or more CPUs and associated memory circuitry. Two or more logical partitions each comprise at a CPU and memory circuit allocation on at least one NUMA node. Each partition respectively runs at least one associated data processing application. The partitions are dynamically managed at runtime to transform the distributed data processing machine from a first partition layout state to a second partition layout state that is optimized for the data processing applications according to whether a given partition will most efficiently execute within a single NUMA node or by spanning across a node boundary. The optimization is based on access latency and bandwidth in the NUMA machine.

    摘要翻译: 管理分区NUMA机器,根据NUMA注意事项动态变换其分区布局状态。 NUMA机器包括通过一个或多个节点间通信链路可操作地互连的两个或更多个NUMA节点。 每个节点包括一个或多个CPU和相关的存储器电路。 两个或多个逻辑分区各自包括在CPU上,并且在至少一个NUMA节点上分配存储器电路。 每个分区分别运行至少一个关联的数据处理应用。 分区在运行时被动态地管理,以将分布式数据处理机器从第一分区布局状态转换到针对数据处理应用程序而优化的第二分区布局状态,根据给定分区是否在单个NUMA节点内最有效地执行, 跨越一个节点边界。 优化基于NUMA机器中的访问延迟和带宽。

    Methods and computer program product for optimizing binaries with coding style formalization
    6.
    发明授权
    Methods and computer program product for optimizing binaries with coding style formalization 失效
    方法和计算机程序产品,用于优化具有编码风格形式化的二进制

    公开(公告)号:US07530060B1

    公开(公告)日:2009-05-05

    申请号:US11970669

    申请日:2008-01-08

    IPC分类号: G06F9/45

    CPC分类号: G06F8/443 G06F8/423

    摘要: Methods and computer program products for providing warnings and hints related to coding conventions using a coding style definition are provided. A source code is received, and a coding style definition is read. The source code is parsed to determine whether the source code adheres to the conventions in the coding style definition. Warnings are provided to indicate where the source code deviates from the coding style definition, if the source code fails to adhere to the conventions in the coding style definition. If the source code correctly adheres to the conventions in the coding style, hints can be provided to the compiler and linker so that they can optimize effectively using information that the compiler and linker would not normally have.

    摘要翻译: 提供了使用编码风格定义提供与编码约定相关的警告和提示的方法和计算机程序产品。 接收到源代码,并读取编码风格定义。 解析源代码以确定源代码是否符合编码风格定义中的约定。 如果源代码不符合编码风格定义中的约定,则提供警告以指示源代码偏离编码风格定义的位置。 如果源代码正确地遵循编码风格中的约定,则可以向编译器和链接器提供提示,以便它们可以有效地使用编译器和链接器通常不具有的信息进行优化。

    Dynamic logical partition management for NUMA machines and clusters
    7.
    发明授权
    Dynamic logical partition management for NUMA machines and clusters 有权
    NUMA机器和集群的动态逻辑分区管理

    公开(公告)号:US08140817B2

    公开(公告)日:2012-03-20

    申请号:US12391827

    申请日:2009-02-24

    IPC分类号: G06F13/14

    CPC分类号: G06F9/5077

    摘要: A partitioned NUMA machine is managed to dynamically transform its partition layout state based on NUMA considerations. The NUMA machine includes two or more NUMA nodes that are operatively interconnected by one or more internodal communication links. Each node includes one or more CPUs and associated memory circuitry. Two or more logical partitions each comprise at a CPU and memory circuit allocation on at least one NUMA node. Each partition respectively runs at least one associated data processing application. The partitions are dynamically managed at runtime to transform the distributed data processing machine from a first partition layout state to a second partition layout state that is optimized for the data processing applications according to whether a given partition will most efficiently execute within a single NUMA node or by spanning across a node boundary. The optimization is based on access latency and bandwidth in the NUMA machine.

    摘要翻译: 管理分区NUMA机器,根据NUMA注意事项动态变换其分区布局状态。 NUMA机器包括通过一个或多个节点间通信链路可操作地互连的两个或更多个NUMA节点。 每个节点包括一个或多个CPU和相关的存储器电路。 两个或多个逻辑分区各自包括在CPU上,并且在至少一个NUMA节点上分配存储器电路。 每个分区分别运行至少一个关联的数据处理应用。 分区在运行时被动态地管理,以将分布式数据处理机器从第一分区布局状态转换到针对数据处理应用程序而优化的第二分区布局状态,根据给定分区是否在单个NUMA节点内最有效地执行, 跨越一个节点边界。 优化基于NUMA机器中的访问延迟和带宽。

    Lock windows for reducing contention
    8.
    发明授权
    Lock windows for reducing contention 有权
    锁定窗口以减少争用

    公开(公告)号:US08701111B2

    公开(公告)日:2014-04-15

    申请号:US12170101

    申请日:2008-07-09

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526

    摘要: Methods and arrangements to assign locks to threads are discussed. Embodiments include transformations, code, state machines or other logic to assign locks to threads. Embodiments may include setting a window of time at the end of a time slice of a thread. The embodiment may also involve prohibiting the thread from acquiring a lock during the window of time, based upon determining that the thread is within the window of time and determining that the thread does not hold any locks. Other embodiments include an apparatus to assign locks to threads and a computer program product to assign locks to threads.

    摘要翻译: 讨论了向线程分配锁的方法和布置。 实施例包括转换,代码,状态机或用于向线程分配锁的其他逻辑。 实施例可以包括在线程的时间片段的末尾设置时间窗口。 该实施例还可以包括基于确定线程在时间窗内并且确定线程不保持任何锁定来禁止线程在时间窗口期间获取锁定。 其他实施例包括向线程分配锁定的装置和用于向线程分配锁定的计算机程序产品。

    Lock Windows for Reducing Contention
    9.
    发明申请
    Lock Windows for Reducing Contention 有权
    锁定Windows以减少争用

    公开(公告)号:US20100011360A1

    公开(公告)日:2010-01-14

    申请号:US12170101

    申请日:2008-07-09

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526

    摘要: Methods and arrangements to assign locks to threads are discussed. Embodiments include transformations, code, state machines or other logic to assign locks to threads. Embodiments may include setting a window of time at the end of a time slice of a thread. The embodiment may also involve prohibiting the thread from acquiring a lock during the window of time, based upon determining that the thread is within the window of time and determining that the thread does not hold any locks. Other embodiments include an apparatus to assign locks to threads and a computer program product to assign locks to threads.

    摘要翻译: 讨论了向线程分配锁的方法和布置。 实施例包括转换,代码,状态机或用于向线程分配锁的其他逻辑。 实施例可以包括在线程的时间片段的末尾设置时间窗口。 该实施例还可以包括基于确定线程在时间窗内并且确定线程不保持任何锁定来禁止线程在时间窗口期间获取锁定。 其他实施例包括向线程分配锁定的装置和用于向线程分配锁定的计算机程序产品。

    Pulling heavy tasks and pushing light tasks across multiple processor units of differing capacity
    10.
    发明授权
    Pulling heavy tasks and pushing light tasks across multiple processor units of differing capacity 有权
    在不同容量的多个处理器单元之间拉扯繁重的任务并推动轻型任务

    公开(公告)号:US08656405B2

    公开(公告)日:2014-02-18

    申请号:US11767570

    申请日:2007-06-25

    IPC分类号: G06F9/46

    摘要: A mechanism is provided for scheduling tasks across multiple processor units of differing capacity. In a multiple processor unit system with processor units of disparate speeds, it is advantageous to have the most processing-intensive tasks run on the processor units with the highest capacity. All tasks are initially scheduled on the lowest capacity processor units. Because processor units with higher capacity are more likely to have idle time, these higher capacity processor units may pull one or more tasks onto themselves from the same or lower capacity processor units. A processor unit will attempt to pull tasks that utilize a larger percentage of the timeslice. When a higher capacity processor unit is overloaded or near capacity, the higher capacity processor unit may push tasks to processor units with the same or lower capacity. A processor unit will attempt to push tasks that utilize a smaller percentage of the timeslice.

    摘要翻译: 提供了一种用于在不同容量的多个处理器单元之间调度任务的机制。 在具有不同速度的处理器单元的多处理器单元系统中,有最大的处理密集型任务在具有最高容量的处理器单元上运行。 所有任务最初都是在最低容量的处理器上进行安排的。 因为具有较高容量的处理器单元更有可能具有空闲时间,所以这些较高容量的处理器单元可以从相同或更低容量的处理器单元将一个或多个任务拉入其自身。 处理器单元将尝试拉动利用更大百分比的时间片的任务。 当较高容量的处理器单元过载或接近容量时,较高容量的处理器单元可将任务推送到具有相同或更低容量的处理器单元。 处理器单元将尝试推送利用较小百分比的时间片的任务。