公开(公告)号：US20120041996A1

公开(公告)日：2012-02-16

申请号：US13136927

申请日：2011-08-15

申请人： Manohar Ayinala ,  Michael J. Brown ,  Keshab K. Parhi

发明人： Manohar Ayinala ,  Michael J. Brown ,  Keshab K. Parhi

IPC分类号： G06F17/14

CPC分类号： G06F17/142 ,  H04L27/263

摘要： The present invention relates to the design and implementation of parallel pipelined circuits for the fast Fourier transform (FFT). In this invention, an efficient way of designing FFT circuits using folding transformation and register minimization techniques is proposed. Based on the proposed scheme, novel parallel-pipelined architectures for the computation of complex fast Fourier transform are derived. The proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The proposed circuits process L consecutive samples from a single-channel signal in parallel. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. The proposed scheme is general and suitable for applications such as communications, biomedical monitoring systems, and high speed OFDM systems.

摘要翻译： 本发明涉及用于快速傅里叶变换（FFT）的并行流水线电路的设计和实现。 在本发明中，提出了使用折叠变换和寄存器最小化技术来设计FFT电路的有效方式。 基于所提出的方案，推导出用于计算复杂快速傅里叶变换的新型并行流水线架构。 所提出的架构利用串行体系结构中利用不足的硬件来推导L并行架构，而不会将硬件复杂度提高一倍。所提出的电路并行处理来自单信道信号的L个连续采样。 可以减少所提出的架构的工作频率，从而降低功耗。 所提出的方案是通用的，适用于通信，生物医学监测系统和高速OFDM系统等应用。