摘要:
The present invention relates to the design and implementation of a three stage computer-aided screening system that analyzes fundus images with varying illumination and fields of view, and generates a severity grade for diabetic retinopathy (DR) using machine learning. In the first stage, bright and red regions are extracted from the fundus image. An optic disc has similar structural appearance as bright lesions, and the blood vessel regions have similar pixel intensity properties as the red lesions. Hence, the region corresponding to the optic disc is removed from the bright regions and the regions corresponding to the blood vessels are removed from the red regions. This leads to an image containing bright candidate regions and another image containing red candidate regions. In the second stage, the bright and red candidate regions are subjected to two-step hierarchical classification. In the first step, bright and red lesion regions are separated from non-lesion regions. In the second step, the classified bright lesion regions are further classified as hard exudates or cotton-wool spots, while the classified red lesion regions are further classified as hemorrhages and micro-aneurysms. In the third stage, the numbers of bright and red lesions per image are combined to generate a DR severity grade. Such a system will help in reducing the number of patients requiring manual assessment, and will be critical in prioritizing eye-care delivery measures for patients with highest DR severity.
摘要:
A K-bit information signal represented by a polynomial U(x) having a degree K−1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P−1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).
摘要:
Turbo decoders may have large decoding latency and low throughput due to iterative decoding. One way to increase the throughput and reduce the latency of turbo decoders is to use high speed decoding schemes. In particular, area-efficient parallel decoding schemes may be used to overcome the decoding latency and throughput associated with turbo decoders. In addition, hybrid parallel decoding schemes may be used in high-level parallelism implementations. Moreover, the area-efficient parallel decoding schemes introduce little or no performance degradation.
摘要:
A joint code-encoder-decoder design approach and circuit architecture design for (3,k)-regular LDPC coding system implementation. The joint design process relies on a high girth (2,k)-regular LDPC code construction. The decoder realizes partly parallel decoding. The encoding scheme only contains multiplications between sparse matrices and vector and multiplication between a very small dense matrix and vector.
摘要:
Digital communications devices having high-speed add-compare-select circuits, and methods for designing the same. The add-compare-select circuits include logic segments separated by delay devices. The separation of the logic segments allows for pipelining of the add-compare-select processes and advantageous circuit retiming. The pipelining and advantageous circuit retiming permit the digital communications devices to be clocked at higher rates than similar digital communications devices having conventional add-compare-select circuits.
摘要:
A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.
摘要:
A method of processing multiple VLC data elements concurrently. A system realizing this method comprises a plurality of encoders under control and a plurality, typically like in number, of decoders under separate, but accorded control. Furthermore, a means of communication from the former to the latter is incorporated in which ordinal and temporal correspondence is established between particular encoders and particular decoders. Encoder control provides an ordered symbol assignment strategy across all encoders. Decoder control detects the encoder assignment strategy and applies it to the task of restoring the original output order among all decoder outputs.
摘要:
A processing means is described for the variable-length encoding of digital signals. The resultant serial encoder admits symbols at data-dependent intervals and progressively releases one bit of encoded output each cycle. The encoder comprises storage, a shifter and a simple pattern tester. Excepting the pattern tester, no arithmetic operations are involved. These three parts are arranged such that processing speed is limited by the greater of the retrieval delay from storage and the delay of the pattern tester. This arrangement is made feasible by an implicit means of codeword length storage. Optimal encoding rates for a serial encoder may hereby be obtained.
摘要:
The present invention relates to design and implementation of low complexity adaptive echo and NEXT cancellers in multi-channel data transmission systems. In this invention, a highly efficient weight update scheme is proposed to reduce the computational cost of the weight update part in adaptive echo and NEXT cancellers. Based on the proposed scheme, the hardware complexity of the weight update part can be further reduced by applying the word-length reduction technique. The proposed scheme is general and suitable for real applications such as design of a low complexity transceiver in 10GBase-T. Different with prior work, this invention considers the complexity reduction in weight update part of the adaptive filters such that the overall complexity of these adaptive cancellers can be significantly reduced.
摘要:
Secure Variable Data Rate Transceivers and methods for implementing Secure Variable Data Rate are presented. An efficient and systematic method and circuit for implementing secure variable data rate transceivers are presented. The SVDR method is based on block ciphers. An index method is presented for minimizing transmission overhead. This allows SVDR to achieve higher security by using the full ciphermode stream.