公开(公告)号：US07394282B2

公开(公告)日：2008-07-01

申请号：US11476949

申请日：2006-06-28

申请人： Manoj K. Sinha ,  Amrish Kontu ,  Binta M. Patel ,  Gian Gerosa

发明人： Manoj K. Sinha ,  Amrish Kontu ,  Binta M. Patel ,  Gian Gerosa

IPC分类号： H03K19/003

CPC分类号： H03K19/018557 ,  H04L25/0298

摘要： A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some aspects, a transition of a strobe signal is then detected, and the termination circuit is coupled to the transmission line in response to the detected transition.

公开(公告)号：US20080001621A1

公开(公告)日：2008-01-03

申请号：US11476949

申请日：2006-06-28

申请人： Manoj K. Sinha ,  Amrish Kontu ,  Binta M. Patel ,  Gian Gerosa

发明人： Manoj K. Sinha ,  Amrish Kontu ,  Binta M. Patel ,  Gian Gerosa

IPC分类号： H03K19/003

CPC分类号： H03K19/018557 ,  H04L25/0298

摘要： A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some aspects, a transition of a strobe signal is then detected, and the termination circuit is coupled to the transmission line in response to the detected transition.

摘要翻译： 系统可以包括检测从传输线路接收的低信号，以及响应于检测到的低信号而将终端电路与传输线路解耦。 在一些方面，随后检测到选通信号的转换，并且响应于检测到的转换，终端电路耦合到传输线。

公开(公告)号：US07379491B2

公开(公告)日：2008-05-27

申请号：US10744085

申请日：2003-12-24

申请人： Steven K. Hsu ,  Ram K. Krishnamurthy ,  Gian Gerosa

发明人： Steven K. Hsu ,  Ram K. Krishnamurthy ,  Gian Gerosa

IPC分类号： H04B3/36

CPC分类号： H04B3/36 ,  H03K3/35625

摘要： A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.

摘要翻译： 提供了一种系统，其包括用于提供两个中继器时钟信号的时钟电路和用于接收两个中继器时钟信号的触发中继器电路和输入数据信号。 触发中继器电路基于两个中继器时钟信号提供输出数据信号。 包括耦合在一起的多个晶体管和反相器的触发中继器电路用作在没有任何完全传输门的情况下传递数据的触发器电路。

公开(公告)号：US20050141599A1

公开(公告)日：2005-06-30

申请号：US10744085

申请日：2003-12-24

申请人： Steven Hsu ,  Ram Krishnamurthy ,  Gian Gerosa

发明人： Steven Hsu ,  Ram Krishnamurthy ,  Gian Gerosa

IPC分类号： H04B3/36

CPC分类号： H04B3/36 ,  H03K3/35625

摘要： A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.

摘要翻译： 提供了一种系统，其包括用于提供两个中继器时钟信号的时钟电路和用于接收两个中继器时钟信号的触发中继器电路和输入数据信号。 触发中继器电路基于两个中继器时钟信号提供输出数据信号。 包括耦合在一起的多个晶体管和反相器的触发中继器电路用作在没有任何全传输门的情况下传递数据的触发器电路。