公开(公告)号：US09998305B2

公开(公告)日：2018-06-12

申请号：US15400647

申请日：2017-01-06

申请人： Rambus Inc.

发明人： Jared L. Zerbe ,  Bruno W. Garlepp ,  Pak S. Chau ,  Kevin S. Donnelly ,  Mark A. Horowitz ,  Stefanos Sidiropoulos ,  Billy W. Garrett, Jr. ,  Carl W. Werner

IPC分类号： H04B17/00 ,  H04L25/03 ,  H04L25/49 ,  H04L25/02 ,  H04L7/033 ,  G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C8/10

CPC分类号： H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

摘要： An integrated circuit device includes an output driver having a data signal terminal, logic circuitry, and a driver circuit coupled to the logic circuitry and data signal terminal. The driver circuit is configured to drive a signal corresponding to a symbol onto the data signal terminal, wherein the symbol is an N-bit symbol, having one of 2N predefined values, N is an integer greater than 1, and the signal corresponding to the symbol has one of 2N signal levels. The driver circuit includes first, second and third driver sub-circuits, each driven by an input corresponding to one or more bits of the N-bit symbol, wherein the second and third driver sub-circuits are weighted, relative to the first driver sub-circuit, to reduce gds distortion in the signal.

公开(公告)号：US20180026525A1

公开(公告)日：2018-01-25

申请号：US15653170

申请日：2017-07-18

申请人： Linear Technology Corporation

发明人： Andrew J. Gardner

IPC分类号： H03H7/01

CPC分类号： H03H7/427 ,  H02M1/44 ,  H03H1/0007 ,  H03H7/0138 ,  H04L12/10 ,  H04L12/40045 ,  H04L25/0272 ,  H04L25/0298

摘要： In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuitry to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

公开(公告)号：US09824728B2

公开(公告)日：2017-11-21

申请号：US14294094

申请日：2014-06-02

申请人： MEDIATEK INC.

发明人： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC分类号： H03K17/16 ,  G11C7/10 ,  G11C29/02 ,  G11C5/06 ,  H03K19/0185 ,  H04L25/02 ,  G06F13/16

CPC分类号： G11C7/109 ,  G06F13/1689 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/028 ,  H03K19/018557 ,  H04L25/0278 ,  H04L25/0298

摘要： A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.

公开(公告)号：US20170286359A1

公开(公告)日：2017-10-05

申请号：US15089531

申请日：2016-04-02

申请人： Steven B. McGowan

发明人： Steven B. McGowan

IPC分类号： G06F13/42 ,  H04L9/32 ,  G06F13/16

CPC分类号： G06F13/4291 ,  G06F13/1673 ,  G06F13/36 ,  G06F13/4295 ,  H04L9/3297 ,  H04L25/0298

摘要： Methods and apparatuses relating to measuring propagation delays through USB retimers are described. In one embodiment, a retimer apparatus includes a receiver to receive a data block and a timestamp for the data block from an upstream device, a buffer to store the data block and the timestamp for transmittal, a controller to modify the timestamp to generate a modified timestamp that includes a time from a receipt of a first portion of the data block in the buffer until a transmittal of the first portion of the data block from the buffer, and a transmitter to transmit the data block and the modified timestamp to a downstream device.

公开(公告)号：US20170286351A1

公开(公告)日：2017-10-05

申请号：US15090363

申请日：2016-04-04

申请人： A-dec, Inc.

发明人： Ryan M. Williams ,  Paul Scott Bontrager

IPC分类号： G06F13/42 ,  G06F13/40 ,  H04L29/08

CPC分类号： G06F13/4265 ,  G06F13/4068 ,  H04L12/40 ,  H04L25/0298 ,  H04L67/104 ,  H04L2012/40215

摘要： A system comprises a plurality of nodes connected in a peer-to-peer network via a communication interface. At least one node of the plurality of nodes comprises a transceiver, at least two connectors, at least one termination resistance module coupled to the transceiver, the at least one termination resistance module providing termination resistance within the node, a first detection circuit coupled to a first connector of the at least two connectors, and a second detection circuit coupled to a second connector of the at least two connectors. The first and second detection circuits are configured to detect that the node is coupled to one or more other nodes in the peer-to-peer network, and automatically adjust the termination resistance based on the detecting.

公开(公告)号：US20170068617A1

公开(公告)日：2017-03-09

申请号：US15355621

申请日：2016-11-18

申请人： MICRON TECHNOLOGY, INC.

发明人： Terry Grunzke

IPC分类号： G06F12/06 ,  G06F13/16

CPC分类号： G06F12/0653 ,  G06F12/0661 ,  G06F13/16 ,  G06F13/18 ,  G11C5/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/06 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14

摘要： Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a termination device during a memory device operation on a memory device of the plurality of memory devices corresponding to a particular address of the memory system, wherein appointing the particular memory device to act as a termination device comprises storing termination information in the particular memory device corresponding to the particular address.

摘要翻译： 用于在存储器系统内终止信号线的方法包括在存储器件操作期间指定多个存储器件的特定存储器件用作终端器件，该存储器器件操作对应于多个存储器器件的特定地址的多个存储器件的存储器器件 存储器系统，其中指定所述特定存储器设备充当终端设备包括将终止信息存储在对应于所述特定地址的所述特定存储设备中。

公开(公告)号：US09544169B2

公开(公告)日：2017-01-10

申请号：US14158675

申请日：2014-01-17

申请人： Rambus Inc.

发明人： Jared L. Zerbe ,  Bruno W. Garlepp ,  Pak S. Chau ,  Kevin S. Donnelly ,  Mark A. Horowitz ,  Stefanos Sidiropoulos ,  Billy W. Garrett, Jr. ,  Carl W. Werner

IPC分类号： H04B17/00 ,  H04L25/03 ,  G11C7/22 ,  G11C11/56 ,  H04L25/02 ,  H04L25/08 ,  H04L25/49 ,  G11C7/10 ,  G11C27/02 ,  H04L7/033

CPC分类号： H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

摘要： An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

摘要翻译： 集成电路器件包括具有输入端的读出放大器，用于接收表示当前位的当前信号。 读出放大器将产生关于当前位的逻辑电平的判定。 该集成电路器件还包括一个电路，用于通过向读出放大器的输入端施加代表先前位的先前信号的一部分来对读出放大器的输入进行预充电。 集成电路器件还包括耦合到读出放大器以输出逻辑电平的锁存器。

公开(公告)号：US09537676B2

公开(公告)日：2017-01-03

申请号：US14497726

申请日：2014-09-26

申请人： Samsung Electronics Co., Ltd.

发明人： Kyung Hoi Koo

IPC分类号： H03K5/08 ,  H04L25/00

CPC分类号： G11C11/4099 ,  G11C7/1084 ,  H03K5/084 ,  H04L25/00 ,  H04L25/0298

摘要： A semiconductor device includes a receiver configured to receive a reference voltage via a first input terminal, receive an input signal via a second input terminal, and generate an output signal by comparing the reference voltage to the input signal with each other. A termination circuit associated with the input signal terminal may be adjusted and a logic threshold voltage may be adjusted to accommodate the adjustment in the termination circuit.

摘要翻译： 半导体器件包括：接收器，被配置为经由第一输入端子接收参考电压，经由第二输入端子接收输入信号，并通过将参考电压与输入信号进行比较来产生输出信号。 可以调节与输入信号端子相关联的终端电路，并且可以调整逻辑阈值电压以适应终端电路中的调整。

公开(公告)号：US20160380607A1

公开(公告)日：2016-12-29

申请号：US14747985

申请日：2015-06-23

申请人： QUALCOMM Incorporated

发明人： Chunchen Liu ,  Po-Hung Chen ,  Zhengyu Duan

IPC分类号： H03H7/01 ,  H03H7/00 ,  H03H7/06

CPC分类号： H03H7/0138 ,  H01P1/24 ,  H03H7/004 ,  H03H7/0123 ,  H03H7/06 ,  H03H7/07 ,  H03H7/383 ,  H03K19/0005 ,  H04B3/14 ,  H04L25/0278 ,  H04L25/0286 ,  H04L25/0298 ,  H04L25/03878

摘要： A signal interconnect includes a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency.

摘要翻译： 信号互连包括传输线，耦合到传输线的终端电路和沿传输线串联耦合的高通滤波器电路。 高通滤波器电路包括并联耦合的第一电阻电路和第一电容电路。 第一电阻电路具有基于高频率的传输线的电阻与低频的传输线的电阻之差的电阻。

公开(公告)号：US20160142053A1

公开(公告)日：2016-05-19

申请号：US14884007

申请日：2015-10-15

申请人： Rambus Inc.

发明人： Huy M. Nguyen ,  Vijay Gadde ,  Benedict Lau

IPC分类号： H03K19/00 ,  H03K19/01 ,  H04L25/02

CPC分类号： H03K19/0005 ,  H03K5/24 ,  H03K19/01 ,  H03K21/08 ,  H04L25/0278 ,  H04L25/0298

摘要： Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.