公开(公告)号：US5867672A

公开(公告)日：1999-02-02

申请号：US646826

申请日：1996-05-21

申请人： Eugene D. Wang ,  Mario F. Au

发明人： Eugene D. Wang ,  Mario F. Au

IPC分类号： G06F5/06 ,  G06F13/38

CPC分类号： G06F5/065

摘要： A buffer IC includes two FIFO buffers accessible in a triple-bus configuration including a bi-directional port, an input port, and an output port. Each of the ports uses a fall-through timing which facilitates interconnection of similar buffer ICs into a chain to expand the depth of a FIFO buffer. Typically, the input and output ports have a data width that differs from the data width of the bi-directional bus the FIFO buffers perform bus matching. One type of bus matching collects data values from the smaller width port to form larger width values for output from the larger port. Another type of bus matching splits data values from the larger width port to form data values for output from the smaller port.

摘要翻译： 缓冲IC包括两个FIFO缓冲器，可在三总线配置中访问，包括双向端口，输入端口和输出端口。 每个端口使用一个通过时间，便于将类似的缓冲器IC互连到链中以扩展FIFO缓冲器的深度。 通常，输入和输出端口的数据宽度与FIFO缓冲器执行总线匹配的双向总线的数据宽度不同。 一种类型的总线匹配从较小的宽度端口收集数据值，以形成较大的宽度值，以从较大的端口输出。 总线匹配的另一种类型是从较大的宽度端口分割数据值，以形成从较小端口输出的数据值。

公开(公告)号：US5789953A

公开(公告)日：1998-08-04

申请号：US655344

申请日：1996-05-29

申请人： Mario F. Au ,  Eugene D. Wang

发明人： Mario F. Au ,  Eugene D. Wang

IPC分类号： H03K5/00 ,  H02M5/40 ,  H03K3/78

CPC分类号： H03K5/00006

摘要： A clock signal generator or frequency multiplier generates an output signal having a frequency which is a non-integer multiple of an input signal frequency. One clock signal generator contains one or more shift registers. A signal generated from a logical combination of bits from the shift registers transitions from high to low or low to high as values in the shift registers shift. The transitions have a pattern which repeats each time values in the shift registers return to their initial states and the initial states stored in the shift registers control the number of transitions per repetition. The frequency of the combined signal is the frequency of the input signal times the ratio of the number of transitions per repetition to the number of shifts per repetition. One embodiment of the invention provides a 1.33x multiple of an input clock signal. Using a 1.33x multiple of a nominally highest frequency input clock signal from a set of input clock signals provides an output clock signal having a frequency greater than any input clock signal in the set even if the frequencies of the input clock signals vary from their nominal frequencies by up to 10%.

摘要翻译： 时钟信号发生器或倍频器产生具有输入信号频率的非整数倍的频率的输出信号。 一个时钟信号发生器包含一个或多个移位寄存器。 从移位寄存器的位的逻辑组合产生的信号从移位寄存器中的值移位，从高到低转换为高。 转换具有每次重复移位寄存器中的值返回到其初始状态的模式，并且存储在移位寄存器中的初始状态控制每次重复的转换次数。 组合信号的频率是输入信号的频率乘以每个重复的转换次数与每次重复的移位数的比率。 本发明的一个实施例提供输入时钟信号的1.33倍。 使用来自一组输入时钟信号的名义上最高频率输入时钟信号的1.33倍倍数，即使输入时钟信号的频率从标称值变化，提供具有大于该组中的任何输入时钟信号的频率的输出时钟信号 频率高达10％。