公开(公告)号：US11417486B2

公开(公告)日：2022-08-16

申请号：US16601112

申请日：2019-10-14

申请人： Hamilton Sundstrand Corporation

发明人： Richard A. Poisson ,  Steven A. Avritch

IPC分类号： H01H51/10 ,  G01R31/327 ,  H01H50/32 ,  H01H51/12 ,  H01H51/27 ,  H03K3/78 ,  H03K5/131

摘要： A method of controlling the behavior of a latching relay includes receiving a configuration signal of either a first behavior signal or a second behavior signal, receiving a power status signal of either a powered or unpowered signal, receiving either a low-to-high or a high-to-low signal command signal, generating latching pulse in response to receiving a powered signal input as the power status signal and a low-to-high signal as the command signal, generating an unlatching pulse in response to receiving a powered signal input as the power status signal and a high-to-low signal as the command signal input, and generating an unlatching pulse in response to receiving the second behavior signal as the configuration signal and the unpowered signal as the power status signal.

公开(公告)号：US10812020B1

公开(公告)日：2020-10-20

申请号：US16544656

申请日：2019-08-19

申请人： Lyten, Inc.

发明人： Michael W. Stowell ,  Tung Van Pham

IPC分类号： H03B9/10 ,  H03K3/78 ,  H03K3/57 ,  H03C5/04 ,  H03L5/02 ,  H01J25/50 ,  H01J37/32 ,  H03K17/082

摘要： Pulsed radiation is generated at a power level that depends on a voltage level, frequency and duty cycle of a pulsed high voltage. A pulsing switch generates the pulsed high voltage from a high voltage and a pulse control signal. The pulsing switch has first and second bi-polar active switches connected in series between a high voltage conductor and a ground conductor. The pulsed high voltage is produced at a connection between the first and second bi-polar active switches when the first and second bi-polar active switches are repeatedly pulsed on and off to alternatingly connect the high voltage conductor and the ground conductor to a pulsed voltage output.

公开(公告)号：US09960754B2

公开(公告)日：2018-05-01

申请号：US12795894

申请日：2010-06-08

申请人： Gongyin Chen ,  Robert Edward Drubka

发明人： Gongyin Chen ,  Robert Edward Drubka

IPC分类号： H03K3/00 ,  H03K3/543 ,  H03K3/64 ,  H03K3/78 ,  H03K7/02

CPC分类号： H03K3/543 ,  H03K3/64 ,  H03K3/78 ,  H03K7/02

摘要： These various embodiments serve to facilitate interlaced amplitude pulsing using a hard-tube type pulse generator having at least one energy-storage unit each comprising at least one energy-storing capacitor. Generally speaking, this comprises controlling an amount of energy withdrawn from the energy-storage unit and provided to an output load to form productive electric pulses by controlling at least one of: (1) energy replenishment; and (2) non-productive energy withdrawal of the energy-storage unit, to thereby achieve a series of productive interlaced amplitude electric pulses.

公开(公告)号：US20130169322A1

公开(公告)日：2013-07-04

申请号：US13713285

申请日：2012-12-13

申请人： STMicroelectronics R&D Co. Ltd. (Shanghai)

发明人： Tina Shen ,  Anderson Yin

IPC分类号： H03K3/78

CPC分类号： H03K3/78 ,  H03K4/023 ,  H04L25/08

摘要： A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

摘要翻译： 本地互连网络（LIN）驱动器电路采用施加到耦合到LIN总线的驱动器晶体管的栅极的充电/放电电流。 充电电流包括恒定的充电电流和额外的软充电电流，而放电电流包括恒定的放电电流和额外的软放电电流。 作为软充电/放电元件的结果，LIN总线上的电磁辐射显着减少。

公开(公告)号：US5789953A

公开(公告)日：1998-08-04

申请号：US655344

申请日：1996-05-29

申请人： Mario F. Au ,  Eugene D. Wang

发明人： Mario F. Au ,  Eugene D. Wang

IPC分类号： H03K5/00 ,  H02M5/40 ,  H03K3/78

CPC分类号： H03K5/00006

摘要： A clock signal generator or frequency multiplier generates an output signal having a frequency which is a non-integer multiple of an input signal frequency. One clock signal generator contains one or more shift registers. A signal generated from a logical combination of bits from the shift registers transitions from high to low or low to high as values in the shift registers shift. The transitions have a pattern which repeats each time values in the shift registers return to their initial states and the initial states stored in the shift registers control the number of transitions per repetition. The frequency of the combined signal is the frequency of the input signal times the ratio of the number of transitions per repetition to the number of shifts per repetition. One embodiment of the invention provides a 1.33x multiple of an input clock signal. Using a 1.33x multiple of a nominally highest frequency input clock signal from a set of input clock signals provides an output clock signal having a frequency greater than any input clock signal in the set even if the frequencies of the input clock signals vary from their nominal frequencies by up to 10%.

摘要翻译： 时钟信号发生器或倍频器产生具有输入信号频率的非整数倍的频率的输出信号。 一个时钟信号发生器包含一个或多个移位寄存器。 从移位寄存器的位的逻辑组合产生的信号从移位寄存器中的值移位，从高到低转换为高。 转换具有每次重复移位寄存器中的值返回到其初始状态的模式，并且存储在移位寄存器中的初始状态控制每次重复的转换次数。 组合信号的频率是输入信号的频率乘以每个重复的转换次数与每次重复的移位数的比率。 本发明的一个实施例提供输入时钟信号的1.33倍。 使用来自一组输入时钟信号的名义上最高频率输入时钟信号的1.33倍倍数，即使输入时钟信号的频率从标称值变化，提供具有大于该组中的任何输入时钟信号的频率的输出时钟信号 频率高达10％。

公开(公告)号：US5703515A

公开(公告)日：1997-12-30

申请号：US620776

申请日：1996-03-22

申请人： Akira Toyama ,  Kazuhiro Shimizu

发明人： Akira Toyama ,  Kazuhiro Shimizu

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/319 ,  H03K3/78 ,  H03K5/13 ,  H03K5/156 ,  H04L7/00 ,  H03K5/04

CPC分类号： H03K5/131 ,  G01R31/31922 ,  G01R31/31928 ,  H03K5/156 ,  G01R31/3191

摘要： A timing generator which receives a rate signal and generates an output signal based on the rate signal, and comprises at least two delay lines for causing delays in the rate signal, a formatter for receiving signals from the delay lines and for determining the rise and fall of an output signal according to such signals from the delay lines, and for generating an output signal, memories for storing delay time data from the delay lines, and a data selector for taking the delay time data from the memories and to switch the delay time data, whereby accurate timing signals are generated utilizing short skew adjustment time.

摘要翻译： 定时发生器，其接收速率信号并基于速率信号产生输出信号，并且包括用于引起速率信号延迟的至少两条延迟线，用于从延迟线接收信号并用于确定上升和下降的格式器 根据来自延迟线的这些信号的输出信号，以及用于产生输出信号的存储器，用于存储来自延迟线的延迟时间数据;以及数据选择器，用于从存储器获取延迟时间数据并切换延迟时间 数据，由此利用短的偏移调整时间产生精确的定时信号。

公开(公告)号：US5630109A

公开(公告)日：1997-05-13

申请号：US487371

申请日：1995-06-07

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G01R31/3183 ,  G01R31/319 ,  H03K3/64 ,  H03K3/78 ,  G06F1/04

CPC分类号： H03K3/78 ,  G01R31/31922

摘要： A frequency and timing generator is presented with high accuracy and frequency resolution and no switching time between different timing cycles for a wide applicable frequency range, wherein the repetition rate of the timing cycles is not limited by the processing speed of the components. The frequency and timing generator according to the invention is accomplished by an apparatus for parallel processing of a series of timing signals comprising at least one processing unit for processing and calculating time values from timing parameters representing the series of timing signals, an output unit for outputting the series of timing signals, and an input unit for inputting the timing parameters. The sequences of n successive timing parameters to be parallelly processed are distributable by the input unit to n processing units. A first time value from a first one of the timing parameters is calculatable by a first one of the processing units, and a succesive time value is calculatable by a succesive one of the processing units from the corresponding successive timing parameter of the sequence and the calculated time value of the respective preceding timing parameter.

摘要翻译： 频率和定时发生器在宽适用频率范围内以高精度和频率分辨率呈现不同定时周期之间的切换时间，其中定时周期的重复率不受组件的处理速度的限制。 根据本发明的频率和定时发生器由一种用于并行处理一系列定时信号的装置来实现，该装置包括至少一个处理单元，用于从表示一系列定时信号的定时参数处理和计算时间值;输出单元，用于输出 一系列定时信号，以及用于输入定时参数的输入单元。 要并行处理的n个连续定时参数的序列可由输入单元分配到n个处理单元。 来自第一个定时参数的第一时间值可由处理单元中的第一个计算，并且随后的时间值可由来自该序列的相应连续定时参数的处理单元中的一个处理单元计算， 时间值。

公开(公告)号：US5524087A

公开(公告)日：1996-06-04

申请号：US367596

申请日：1995-01-03

申请人： Masanobu Kawamura ,  Hiroyuki Kida ,  Seiji Kamada ,  Toshiyuki Tojo ,  Takeshi Ohkubo ,  Hiroyuki Matsuura ,  Naoki Yashiki ,  Nobuo Shibasaki

发明人： Masanobu Kawamura ,  Hiroyuki Kida ,  Seiji Kamada ,  Toshiyuki Tojo ,  Takeshi Ohkubo ,  Hiroyuki Matsuura ,  Naoki Yashiki ,  Nobuo Shibasaki

IPC分类号： H03B28/00 ,  G06F1/035 ,  H03K3/78 ,  H03K4/02 ,  H03K4/92 ,  H04L29/10 ,  G06F1/02

CPC分类号： G06F1/035

摘要： A variable wave forming circuit is provided which produces signals of various waveforms (e.g., sine, triangular or trapezoidal waves) and various frequencies. A random access memory (memory means) 121 to store wave formation information on waveform is provided. According to the wave formation information stored in the memory means, the updating or keeping of a digital value in an increment/decrement circuit 123 is controlled and the digital value is digital/analog-converted by a digital/analog (D/A) conversion circuit 124, which is controlled by a digital value control means that includes the increment/decrement circuit 123. By writing appropriate wave formation information into the memory means, it is possible to produce signals of desired waveforms.

摘要翻译： 提供了一种产生各种波形（例如，正弦波，三角波或梯形波）和各种频率的信号的可变波形成电路。 提供了存储关于波形的波形信息的随机存取存储器（存储装置）121。 根据存储在存储装置中的波形信息，控制增量/减量电路123中的数字值的更新或保持，并且通过数字/模拟（D / A）转换对数字值进行数/模转换 电路124由包括增量/递减电路123的数字值控制装置控制。通过将适当的波形形成信息写入存储装置，可以产生所需波形的信号。

公开(公告)号：US5488646A

公开(公告)日：1996-01-30

申请号：US409108

申请日：1995-03-23

申请人： Anthony M. Jones ,  David A. Barnes

发明人： Anthony M. Jones ,  David A. Barnes

IPC分类号： G06F1/08 ,  H03K5/15 ,  H03K21/02 ,  H03K3/78 ,  H03K21/10

CPC分类号： H03K5/15026 ,  G06F1/08

摘要： The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

摘要翻译： 本发明公开了一种与L个计数器结合实现L相时钟的方法和装置，其中L为整数，以L为可调整的频率进行计数。

公开(公告)号：US5390192A

公开(公告)日：1995-02-14

申请号：US801308

申请日：1991-12-02

申请人： Takanori Fujieda

发明人： Takanori Fujieda

IPC分类号： H03K3/78 ,  G01R31/28 ,  G01R31/3181 ,  G06F11/00

CPC分类号： G01R31/31813

摘要： A high speed pattern generator includes a programmable counter, n pattern generating circuits, a multiplexer and a control memory. The programmable counter divides a frequency of a system clock signal by n (n.gtoreq.2) to thereby generate a clock signal having a frequency of 1/n of the frequency of the system clock and a select signal representative of a count output of said programmable counter. The n pattern generating circuits operate at a frequency determined by the clock signal and produce a pattern signal as a function. A multiplexer converts patterns generated by the n pattern generating circuits into a time-serial pattern in response to the select signal for sequentially selecting outputs of the n pattern generating circuits to thereby output a fast pattern. A control memory which operates at a frequency determined by the clock signal produces a control signal to periodically switch a frequency division ratio of the programmable counter between a plurality of ratios. When the frequency division ratio is changed, generation of any dummy pattern can be suppressed.

摘要翻译： 高速模式发生器包括可编程计数器，n个模式产生电路，多路复用器和控制存储器。 可编程计数器将系统时钟信号的频率除以n（n> / = 2），从而生成具有系统时钟的频率的1 / n的频率的时钟信号和表示系统时钟的计数输出的选择信号 所述可编程计数器。 n个图案生成电路以由时钟信号确定的频率工作，并且产生作为功能的图案信号。 复用器响应于用于顺序地选择n个图案生成电路的输出的选择信号，将由n个图案生成电路生成的图案转换为时间串行图案，从而输出快速图案。 以由时钟信号确定的频率工作的控制存储器产生控制信号，以周期性地切换多个比率之间的可编程计数器的分频比。 当分频比改变时，可以抑制任何虚拟图案的产生。