公开(公告)号：US08649211B2

公开(公告)日：2014-02-11

申请号：US13528528

申请日：2012-06-20

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C11/00

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。

公开(公告)号：US08379447B2

公开(公告)日：2013-02-19

申请号：US12827084

申请日：2010-06-30

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C16/06

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。

公开(公告)号：US20120257441A1

公开(公告)日：2012-10-11

申请号：US13528528

申请日：2012-06-20

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C29/00 ,  G11C11/00

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。

公开(公告)号：US20120002471A1

公开(公告)日：2012-01-05

申请号：US12827084

申请日：2010-06-30

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C16/06 ,  G11C29/00

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。