公开(公告)号：US08649211B2

公开(公告)日：2014-02-11

申请号：US13528528

申请日：2012-06-20

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C11/00

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。

公开(公告)号：US20090252269A1

公开(公告)日：2009-10-08

申请号：US12060886

申请日：2008-04-02

申请人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

发明人： Sarma S. Gunturi ,  Jawaharlal Tangudu ,  Sthanunathan Ramakrishnan ,  Jayawardan Janardhanan ,  Debapriya Sahu ,  Subhashish Mukherjee

IPC分类号： H04L7/00

CPC分类号： H04L27/362 ,  H04L7/0331

摘要： A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from π/2, π/4, π/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of π/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

摘要翻译： 一种在数字控制振荡器（DCO）中实现减少的调制范围要求的方法，其被部署为DRP（数字无线电处理器）的一部分并被调谐到具有操作信道中心频率的调谐频率范围，其中连续样本之间的相位差 被称为FCW（频率控制字），使用数字修改和限制FCW的步骤，使得FCW不超过已知的FCW阈值，例如从pi / 2，pi / 4，pi / 8选择并重新分配 FCW同时保持相位的累积和，并且没有显着的EVM（误差矢量幅度）劣化。 FCW阈值可以任​​意选择，不需要以pi / 2n的形式。 该方法使用FCW限制算法，其降低DCO的电源电压灵敏度，并且能够显着减小电容器组的面积，否则将需要它。

公开(公告)号：US08379447B2

公开(公告)日：2013-02-19

申请号：US12827084

申请日：2010-06-30

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C16/06

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。

公开(公告)号：US06596584B1

公开(公告)日：2003-07-22

申请号：US09692691

申请日：2000-10-19

申请人： Sarma S. Gunturi ,  Paul A. Chintapalli

发明人： Sarma S. Gunturi ,  Paul A. Chintapalli

IPC分类号： H01L218234

CPC分类号： H01L27/115 ,  G11C16/0416

摘要： A method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region. The method also includes forming an isolation structure in the semiconductor substrate that crosses the source, drain, and channel regions of the semiconductor substrate. The method also includes forming a continuous stack structure outwardly from the channel region of the semiconductor substrate and the isolation structure. The method includes depositing a bottom anti-reflective layer over the semiconductor substrate, the isolation structure and the stack structure to substantially uniformly planarize the semiconductor substrate and the isolation structure. The method further includes depositing a photoresist layer over select portions of the bottom anti-reflective layer and the continuous stack structure to form a self-aligned source pattern using a photo mask. The method includes etching the isolation structure and the bottom anti-reflective layer corresponding to the self aligned source pattern using a low selectivity etch process to remove a portion of the isolation structure and etching a remaining portion of the isolation structure using high selectivity etch process.

摘要翻译： 制造具有自对准源的快闪存储器件的方法包括：提供具有通过沟道区域与漏极区域分离的源极区域的半导体衬底。 该方法还包括在半导体衬底中形成与半导体衬底的源极，漏极和沟道区交叉的隔离结构。 该方法还包括从半导体衬底的沟道区域和隔离结构向外形成连续堆叠结构。 该方法包括在半导体衬底上沉积底部抗反射层，隔离结构和堆叠结构以使半导体衬底和隔离结构基本均匀地平坦化。 该方法还包括在底部抗反射层和连续堆叠结构的选定部分上沉积光致抗蚀剂层，以使用光掩模形成自对准源图案。 该方法包括使用低选择性蚀刻工艺来蚀刻对应于自对准源图案的隔离结构和底部抗反射层，以去除隔离结构的一部分，并使用高选择性蚀刻工艺蚀刻隔离结构的剩余部分。

公开(公告)号：US6071779A

公开(公告)日：2000-06-06

申请号：US225436

申请日：1999-01-05

申请人： Freidoon Mehrad ,  Sarma S. Gunturi ,  Cetin Kaya ,  Kyle A. Picone

发明人： Freidoon Mehrad ,  Sarma S. Gunturi ,  Cetin Kaya ,  Kyle A. Picone

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a semiconductor substrate (52) having a source region (60) separated from a drain region (62) by a channel region (64). An isolation structure (70) may be formed in the semiconductor substrate (52). The isolation structure (70) may cross the source region (60), the drain region (62), and the channel region (64) of the semiconductor substrate (52). An isolation dielectric material (78) may be formed within the isolation structure (70). A continuous stack structure (50) may be formed outwardly from the channel region (64) of the semiconductor substrate (52) and the isolation structure (70). A first photomask (100) may be formed outwardly from the continuous stack structure (50) and the semiconductor substrate (52). The first photomask (100) may expose a strip region (102) of the semiconductor substrate (52) and the isolation structure (70). The isolation dielectric material (78) may be removed from the exposed portion the isolation structure (70) to expose the semiconductor substrate (52). A dopant may be implanted into the exposed semiconductor substrate (52) to form the source line (24) in the semiconductor device.

摘要翻译： 提供一种制造具有包括源极线（24）的存储器阵列（9）的半导体器件的方法。 形成源极线（24）的方法可以包括提供具有通过沟道区（64）与漏极区（62）分离的源极区（60）的半导体衬底（52）。 隔离结构（70）可以形成在半导体衬底（52）中。 隔离结构（70）可以穿过半导体衬底（52）的源极区域（60），漏极区域（62）和沟道区域（64）。 隔离电介质材料（78）可以形成在隔离结构（70）内。 可以从半导体衬底（52）的沟道区（64）和隔离结构（70）向外形成连续堆叠结构（50）。 可以从连续堆叠结构（50）和半导体衬底（52）向外形成第一光掩模（100）。 第一光掩模（100）可以暴露半导体衬底（52）和隔离结构（70）的条带区域（102）。 隔离电介质材料（78）可以从隔离结构（70）的暴露部分去除以暴露半导体衬底（52）。 可以将掺杂剂注入到暴露的半导体衬底（52）中以在半导体器件中形成源极线（24）。

公开(公告)号：US08477631B2

公开(公告)日：2013-07-02

申请号：US12546867

申请日：2009-08-25

申请人： Sthanunathan Ramakrishnan ,  Bijoy Bhukania ,  Jawaharlal Tangudu ,  Sarma S Gunturi ,  Jaiganesh Balakrishnan ,  Rakesh Kumar ,  Abhijit Kumar Das ,  Yogesh Darwhekar

发明人： Sthanunathan Ramakrishnan ,  Bijoy Bhukania ,  Jawaharlal Tangudu ,  Sarma S Gunturi ,  Jaiganesh Balakrishnan ,  Rakesh Kumar ,  Abhijit Kumar Das ,  Yogesh Darwhekar

IPC分类号： H04B7/00

CPC分类号： H04L12/12 ,  H04W24/00 ,  H04W28/18 ,  H04W52/028 ,  H04W84/12 ,  H04W84/18 ,  H04W88/02 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/162 ,  Y02D70/23

摘要： A receiver in a packet based communication system includes a programmable block and a detection block that detects at least one of an operating condition of the receiver and a protocol condition of the communication system. Further, the receiver includes a control circuit coupled to the programmable block that controls the programmable block to transition to a set of radio modes according to at least one of the operating condition and the protocol condition.

摘要翻译： 基于分组的通信系统中的接收机包括可编程块和检测接收机的操作条件和通信系统的协议条件中的至少一个的检测块。 此外，接收机包括耦合到可编程块的控制电路，其根据操作条件和协议条件中的至少一个控制可编程块向一组无线电模式转变。

公开(公告)号：US20120257441A1

公开(公告)日：2012-10-11

申请号：US13528528

申请日：2012-06-20

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C29/00 ,  G11C11/00

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。

公开(公告)号：US20120002471A1

公开(公告)日：2012-01-05

申请号：US12827084

申请日：2010-06-30

申请人： Mark A. Dexter ,  Sarma S. Gunturi

发明人： Mark A. Dexter ,  Sarma S. Gunturi

IPC分类号： G11C16/06 ,  G11C29/00

CPC分类号： G11C29/702 ,  G11C16/0408

摘要： An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss.

摘要翻译： 包含具有存储器位的存储器阵列的集成电路和用于读取存储器位的逻辑状态的差分读出放大器。 该集成电路还包含在通过路径中将位线耦合到Vss的冗余通孔。 而且，该集成电路包含从位线到Vss的通路中具有冗余通孔的闪存存储器位。

公开(公告)号：US07817736B2

公开(公告)日：2010-10-19

申请号：US11770806

申请日：2007-06-29

申请人： Sarma S Gunturi ,  Jawaharlal Tangudu ,  Nagasatya Srikanth Puvvada

发明人： Sarma S Gunturi ,  Jawaharlal Tangudu ,  Nagasatya Srikanth Puvvada

IPC分类号： H04L27/28

CPC分类号： H04L27/2657 ,  H04L27/2671 ,  H04L27/2672 ,  H04L27/2675

摘要： A multi-carrier (MC) receiver receives a multi-carrier signal containing data symbols as well as pilot symbols. The MC receiver estimates a carrier frequency offset in a downconverted base-band multi-carrier signal in the frequency domain based on deviations of one or more characteristics of the pilot signals from predetermined values, and corrects for the offset in the time domain. In an embodiment, a second order phase locked loop (PLL) estimates the phase of the pilot signals to determine the carrier frequency offset. Changes in pilot phases caused due to the time domain correction are cancelled to allow the PLL to minimize deviations from the lock position.

摘要翻译： 多载波（MC）接收机接收包含数据符号以及导频符号的多载波信号。 MC接收机基于来自预定值的导频信号的一个或多个特性的偏差来估计频域中的下变频基带多载波信号中的载波频率偏移，并校正时域中的偏移。 在一个实施例中，二阶锁相环（PLL）估计导频信号的相位以确定载波频率偏移。 由于时域校正引起的导频相位的变化被取消，以允许PLL最小化与锁定位置的偏差。

公开(公告)号：US4846928A

公开(公告)日：1989-07-11

申请号：US224205

申请日：1988-07-22

申请人： Steven B. Dolins ,  Aditya Srivastava ,  Bruce E. Flinchbaugh ,  Sarma S. Gunturi ,  Thomas W. Lassiter ,  Robert L. Love

发明人： Steven B. Dolins ,  Aditya Srivastava ,  Bruce E. Flinchbaugh ,  Sarma S. Gunturi ,  Thomas W. Lassiter ,  Robert L. Love

IPC分类号： H01J37/32

CPC分类号： H01J37/32935

摘要： An improved apparatus and process for detecting aberrations in production process operations is provided. In one embodiment, operations of a plasma etch reactor (10) are monitored to detect aberrations in etching operations. A reference end-point trace (EPT) is defined (62) for the etch process. Regions are defined in the reference end-point trace (70) and characteristics and tolerances for each region are defined (72-80). The etcher is run and an actual EPT is obtained (82) from the running of the etcher. The actual EPT is analyzed to identify proposed regions of the actual EPT (86), and then the proposed regions of the actual EPT are matched with regions of the reference EPT (96). The system employs a series of heuristic functions in matching proposed regions of the actual EPT with regions of the reference EPT. Characteristics of the matched regions of the actual end-point trace are compared (66) with characteristics of the corresponding regions of the reference end-point trace to determine whether aberrations have occurred during the etch process. The invention provides for an improved matching and improved comparison of actual end-point traces with reference end-point traces.

摘要翻译： 提供了一种用于检测生产过程操作中的像差的改进的装置和过程。 在一个实施例中，监测等离子体蚀刻反应器（10）的操作以检测蚀刻操作中的像差。 为蚀刻过程定义了参考端点轨迹（EPT）（62）。 区域在参考终点轨迹（70）中定义，每个区域的特征和公差被定义（72-80）。 蚀刻器运行，从蚀刻器的运行获得实际的EPT（82）。 分析实际的EPT以识别实际EPT（86）的建议区域，然后将实际EPT的建议区域与参考EPT（96）的区域匹配。 该系统采用一系列启发式功能，将实际EPT的建议区域与参考EPT的区域进行匹配。 将实际端点迹线的匹配区域的特征与参考端点迹线的相应区域的特性进行比较（66），以确定在蚀刻过程期间是否发生了像差。 本发明提供了改进的匹配和改进的实际端点迹线与参考端点迹线的比较。