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10 条记录 (耗时 0.017 秒)

    Trading propensity-based clustering of circuit elements in a circuit design
    1.
    发明申请
    Trading propensity-based clustering of circuit elements in a circuit design 有权
    电路设计中电路元件的交易倾向聚类

    公开(公告)号：US20070260949A1

    公开(公告)日：2007-11-08

    申请号：US11348907

    申请日：2006-02-07

    申请人： Mark Fredrickson ,  Chad McBride

    发明人： Mark Fredrickson ,  Chad McBride

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318357 ,  G01R31/318536 ,  G06F17/5045

    摘要： An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.

    摘要翻译： 装置，程序产品和方法利用基于交易倾向的聚类算法来生成电路元件到集群或组的分配，以优化多个集群的空间分布。 例如，可以使用基于交易倾向的聚类来将电路元件（诸如具有扫描功能的锁存器）分配给单独的扫描链，以优化用于集成电路设计的扫描架构中的扫描链的布局。

    Heuristic clustering of circuit elements in a circuit design
    2.
    发明申请
    Heuristic clustering of circuit elements in a circuit design 失效
    电路设计中电路元件的启发式聚类

    公开(公告)号：US20070186199A1

    公开(公告)日：2007-08-09

    申请号：US11348970

    申请日：2006-02-07

    申请人： Mark Fredrickson ,  Glen Handlogten ,  Chad McBride

    发明人： Mark Fredrickson ,  Glen Handlogten ,  Chad McBride

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.

    摘要翻译： 一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。 例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

    Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree
    3.
    发明申请
    Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree 失效
    用于设计用于匹配时钟树门控部分的逻辑扫描链的方法，装置和计算机程序产品

    公开(公告)号：US20070168797A1

    公开(公告)日：2007-07-19

    申请号：US11191417

    申请日：2005-07-28

    申请人： Mark Fredrickson ,  Glen Handlogten ,  Steven Jones ,  Chad McBride

    发明人： Mark Fredrickson ,  Glen Handlogten ,  Steven Jones ,  Chad McBride

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318552 ,  G01R31/318583

    摘要： Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.

    摘要翻译： 提供了用于设计用于匹配时钟树的门控部分的逻辑扫描链的方法，装置和计算机程序产品。 时钟树包括多个部分，每个部分包括接收用于特定扫描链的全局时钟和链专用时钟控制信号的输入的门。 定义了多个扫描链，每个扫描链包括多个闩锁。 每个扫描链锁存器连接到相应的链专用时钟树部分。

    Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout
    4.
    发明申请
    Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout 失效
    基于物理布局的集成电路设计的功能定义的自动背面注释

    公开(公告)号：US20070186204A1

    公开(公告)日：2007-08-09

    申请号：US11348877

    申请日：2006-02-07

    申请人： Mark Fredrickson ,  Glen Handlogten ,  Chad McBride

    发明人： Mark Fredrickson ,  Glen Handlogten ,  Chad McBride

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.

    摘要翻译： 一种装置，程序产品和方法基于从功能定义生成的物理布局自动地回溯电路设计的功能定义。 电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号 功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。

    Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain
    5.
    发明申请
    Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain 有权
    用于实现扫描链特定控制信号作为扫描链的一部分的方法，装置和计算机程序产品

    公开(公告)号：US20070101221A1

    公开(公告)日：2007-05-03

    申请号：US11266744

    申请日：2005-11-03

    申请人： Mark Fredrickson ,  Scott Frei ,  Steven Jones

    发明人： Mark Fredrickson ,  Scott Frei ,  Steven Jones

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318544 ,  G01R31/318536

    摘要： A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes a logic gate for combining a global clock control (THOLD) signal and the scan control signal. The scan control signal is routed around the register latch and including in a scan output vector including scan data output. Chain-specific control signals are eliminated from a clock control signal distribution tree used with the scan chain of the invention.

    摘要翻译： 提供了一种用于实现扫描链特定控制信号作为扫描链的组成部分的方法，装置和计算机程序产品。 包括扫描数据输入和扫描控制信号的扫描输入矢量被施加到形成扫描链的寄存器锁存器。 寄存器锁存器包括用于组合全局时钟控制（THOLD）信号和扫描控制信号的逻辑门。 扫描控制信号围绕寄存器锁存器路由并包括在包括扫描数据输出的扫描输出向量中。 从与本发明的扫描链一起使用的时钟控制信号分配树中消除链特定控制信号。

    Methods and apparatus for reducing command processing latency while maintaining coherence
    7.
    发明申请
    Methods and apparatus for reducing command processing latency while maintaining coherence 审中-公开
    减少命令处理延迟同时保持一致性的方法和装置

    公开(公告)号：US20070186052A1

    公开(公告)日：2007-08-09

    申请号：US11348969

    申请日：2006-02-07

    申请人： Jeffrey Brown ,  Scott Clark ,  Mark Fredrickson ,  Charles Johns ,  David Krolak

    发明人： Jeffrey Brown ,  Scott Clark ,  Mark Fredrickson ,  Charles Johns ,  David Krolak

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0804 ,  G06F12/0831

    摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。 第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。 响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。 提供了许多其他方面。

    METHODS AND APPARATUS FOR REDUCING COMMAND PROCESSING LATENCY WHILE MAINTAINING COHERENCE
    8.
    发明申请
    METHODS AND APPARATUS FOR REDUCING COMMAND PROCESSING LATENCY WHILE MAINTAINING COHERENCE 失效
    在保持协调的同时减少指令处理的方法和装置

    公开(公告)号：US20080052472A1

    公开(公告)日：2008-02-28

    申请号：US11846697

    申请日：2007-08-29

    申请人： Jeffrey Brown ,  Scott Clark ,  Mark Fredrickson ,  Charles Johns ,  David Krolak

    发明人： Jeffrey Brown ,  Scott Clark ,  Mark Fredrickson ,  Charles Johns ,  David Krolak

    IPC分类号： G06F12/16

    CPC分类号： G06F12/0804 ,  G06F12/0831

    摘要： In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including memory addresses available to a system; and (2) arranging the memory addresses into a plurality of groups. At least one of the groups does not require the system, in response to a command that requires access to a memory address in the group from a bus unit, to get permission from all remaining bus units included in the system to maintain memory coherence. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种在维持存储器一致性的同时降低命令处理等待时间的方法。 第一种方法包括以下步骤：（1）提供包括可用于系统的存储器地址的存储器映射; 和（2）将存储器地址排列成多个组。 响应于需要访问来自总线单元的组中的存储器地址的命令，组中的至少一个不需要系统以从包括在系统中的所有剩余总线单元获得许可以维持存储器一致性。 提供了许多其他方面。

    Fair hierarchical arbiter
    9.
    发明申请
    Fair hierarchical arbiter 有权

    公开(公告)号：US20070073949A1

    公开(公告)日：2007-03-29

    申请号：US11239615

    申请日：2005-09-29

    申请人： Mark Fredrickson ,  David Krolak

    发明人： Mark Fredrickson ,  David Krolak

    IPC分类号： G06F13/14

    CPC分类号： G06F13/362

    摘要： A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request bits, the valid request bits providing information about which requestor originated a current winning request, and, in some embodiments, about how many separate requesters are arbitrated by that particular arbitration mechanism. The fair hierarchical arbiter outputs requests from the total set of separate requestors in a round robin order.