Technique for improving negative potential immunity of an integrated circuit
    1.
    发明授权
    Technique for improving negative potential immunity of an integrated circuit 有权
    提高集成电路的负电位抗扰度的技术

    公开(公告)号:US07436223B2

    公开(公告)日:2008-10-14

    申请号:US11261310

    申请日:2005-10-28

    IPC分类号: H03B1/00

    CPC分类号: H03K17/0822 H01L29/7816

    摘要: An integrated circuit (IC) with negative potential protection includes a switch, a gate drive circuit and a comparator. The switch includes a double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The switch also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket. An output of the gate drive circuit is coupled across a gate and a source of the switch. An output of the comparator is coupled to a second input of the gate drive circuit and a first input of the comparator receives a reference signal. A second input of the comparator is coupled to the epitaxial pocket. The comparator provides a turn-on signal that causes the switch to conduct current, when a signal at the second input of the comparator is below the reference signal.

    摘要翻译: 具有负电位保护的集成电路(IC)包括开关,栅极驱动电路和比较器。 该开关包括形成在第二型衬底中的第一型外延袋中形成的双扩散金属氧化物半导体(DMOS)单元。 开关还包括形成在衬底中以隔离第一类型外延袋的第二类型+隔离环。 栅极驱动电路的输出端跨越开关的栅极和源极耦合。 比较器的输出耦合到栅极驱动电路的第二输入,比较器的第一输入接收参考信号。 比较器的第二输入耦合到外延袋。 当比较器的第二输入端的信号低于参考信号时,比较器提供导通开关导通电流的导通信号。