公开(公告)号：US20140281406A1

公开(公告)日：2014-09-18

申请号：US13843558

申请日：2013-03-15

申请人： Martin DIXON ,  Baiju PATEL ,  Rajeev GOPALAKRISHNA

发明人： Martin DIXON ,  Baiju PATEL ,  Rajeev GOPALAKRISHNA

IPC分类号： G06F9/38

CPC分类号： G06F9/3016 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30076 ,  G06F9/3802 ,  G06F9/3838 ,  G06F9/3861

摘要： A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.

摘要翻译： 描述了处理器在指令执行流水线内具有功能单元。 功能单元具有用于确定来自较大源数据大小的实质数据是否适合实质数据要流向的较小数据大小的电路。

公开(公告)号：US20130188789A1

公开(公告)日：2013-07-25

申请号：US13791224

申请日：2013-03-08

申请人： Shay GUERON ,  Martin DIXON ,  Srinivas CHENNUPATY ,  Mayank BOMB ,  Brent BOSWELL

发明人： Shay GUERON ,  Martin DIXON ,  Srinivas CHENNUPATY ,  Mayank BOMB ,  Brent BOSWELL

IPC分类号： H04L9/28

CPC分类号： H04L9/28 ,  G06F9/30007 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

摘要： An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.