公开(公告)号：US20070079110A1

公开(公告)日：2007-04-05

申请号：US11240637

申请日：2005-10-03

申请人： Martinus Wezelenburg ,  Dirk Duerinckx ,  Jan Guffens

发明人： Martinus Wezelenburg ,  Dirk Duerinckx ,  Jan Guffens

IPC分类号： G06F9/40

CPC分类号： G06F9/3802

摘要： An interface operable to request instructions from a data store storing instructions of an application to be processed by a data processor, and operable to receive and transmit said instructions to said data processor, said interface comprising: an input operable to receive said instructions from said data store via at least one input bus; a buffer operable to store said received instructions; an output operable to output said instructions to said data processing apparatus via at least one output bus; a control signal input operable to receive a control signal; and a buffer controller operable to: control said buffer to request an instruction subsequent to a previously received instruction within an instruction stream of said application from said data store in response to detection of no control signal on said control signal input and to detection of available buffer storage capacity; and in response to a control signal received at said control signal input, said controller is operable to control at least one of input and storage of instructions within said interface in order to seek to reduce instruction movement through said input.

摘要翻译： 一种可操作以从存储由数据处理器处理的应用的指令的数据存储器请求指令的接口，并且可操作以从所述数据处理器接收和发送所述指令，所述接口包括：可操作以从所述数据接收所述指令的输入 通过至少一个输入总线存储; 缓冲器，用于存储所述接收到的指令; 输出，用于经由至少一个输出总线将所述指令输出到所述数据处理装置; 控制信号输入，用于接收控制信号; 以及缓冲器控制器，其可操作用于：响应于所述控制信号输入上没有控制信号的检测和所述控制信号输入的检测，控制所述缓冲器以从所述数据存储器请求在所述应用的指令流之内的先前接收到的指令之后的指令 存储容量; 并且响应于在所述控制信号输入处接收到的控制信号，所述控制器可操作以控制所述接口内的指令的输入和存储中的至少一个，以便寻求减少通过所述输入的指令移动。

公开(公告)号：US20060271712A1

公开(公告)日：2006-11-30

申请号：US11403201

申请日：2006-04-13

申请人： Martinus Wezelenburg ,  Johan Matterne ,  Dirk Duerinckx ,  Sven Wambedq

发明人： Martinus Wezelenburg ,  Johan Matterne ,  Dirk Duerinckx ,  Sven Wambedq

IPC分类号： G06F13/28

CPC分类号： G06F9/4843 ,  G06F9/5016

摘要： A data processing apparatus and method of operation of such a data processing apparatus are disclosed. The data processing apparatus has a main processing unit operable to perform a plurality of data processing tasks, and a data engine for performing a number of those tasks on behalf of the main processing unit. At least one shared resource is allocatable to the data engine by the main processing unit for use by the data engine when performing data processing tasks on behalf of the main processing unit. The data engine comprises a data engine core for performing the tasks, and a data engine subsystem configurable by the main processing unit and arranged to manage communication between the data engine core and an allocated shared resource. The data engine core comprises a resource manager unit for acting as a master device with respect to the data engine subsystem in order to manage use of the allocated shared resource. It has been found that such an approach provides a particularly efficient implementation of a data engine within a data processing apparatus, which reduces the need for re-writing of existing code to enable it to be executed on such a data processing apparatus.

摘要翻译： 公开了这种数据处理装置的数据处理装置和操作方法。 数据处理装置具有可操作以执行多个数据处理任务的主处理单元，以及代表主处理单元执行多个任务的数据引擎。 至少一个共享资源可由主处理单元分配给数据引擎，供数据引擎在代表主处理单元执行数据处理任务时使用。 数据引擎包括用于执行任务的数据引擎核心以及由主处理单元配置并被配置为管理数据引擎核心和所分配的共享资源之间的通信的数据引擎子系统。 数据引擎核心包括用于充当相对于数据引擎子系统的主设备的资源管理器单元，以便管理所分配的共享资源的使用。 已经发现，这种方法提供了在数据处理装置内的数据引擎的特别有效的实施方式，这减少了对现有代码的重写的需要，以使其能够在这样的数据处理装置上执行。

公开(公告)号：US20060253649A1

公开(公告)日：2006-11-09

申请号：US11121185

申请日：2005-05-04

申请人： Martinus Wezelenburg

发明人： Martinus Wezelenburg

IPC分类号： G06F12/00

CPC分类号： G06F9/3879 ,  G06F9/4843 ,  G06F9/5011

摘要： A local FIFO memory 2 is provided within a local RAM memory 4 to provide access to source data values. A local controller 10 manages the asynchronous fetching of source data values to the local FIFO memory 2 and the optional writing back of these data values after processing to a source/sync memory 32. One or more local head pointers and one or more local tail pointers are used by the local memory controller 10 to manage storage within the local FIFO memory 2 which is configured as a circular buffer; The remaining space within the local RAM 4 may be used for further data and the partitioning between FIFO operation and further data storage is programmable such that the same memory storage 2 can be used for multiple purposes as required.

摘要翻译： 本地FIFO存储器2设置在本地RAM存储器4内，以提供对源数据值的访问。 本地控制器10管理对本地FIFO存储器2的源数据值的异步取出以及在对源/同步存储器32的处理之后可选择地回写这些数据值。 本地存储器控制器10使用一个或多个本地头指针和一个或多个局部尾指针来管理被配置为循环缓冲器的本地FIFO存储器2内的存储器; 本地RAM 4中的剩余空间可用于进一步的数据，并且FIFO操作与进一步的数据存储之间的划分是可编程的，使得相同的存储器2可以根据需要用于多个目的。

公开(公告)号：US20070011364A1

公开(公告)日：2007-01-11

申请号：US11173162

申请日：2005-07-05

申请人： Martinus Wezelenburg

发明人： Martinus Wezelenburg

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A direct memory access controller is provided that is operable to perform a data transfer to transfer target data from a source to a destination. The direct memory access controller comprises an address generator having a set of iterators comprising a sample iterator, at least one frame iterator and at least one block iterator. The address generator is operable to generate a sequence of non-contiguous addresses by performing nested iteration of the set of iterators in accordance with an iterator hierarchy. The direct memory access controller is operable to perform the data transfer such that the destination data format differs from the source data format.

摘要翻译： 提供了直接存储器访问控制器，其可操作以执行数据传送以将目标数据从源传送到目的地。 直接存储器存取控制器包括地址生成器，该地址生成器具有一组迭代器，该迭代器包括样本迭代器，至少一个帧迭代器和至少一个块迭代器。 地址生成器可操作以通过根据迭代器层次来执行迭代器集合的嵌套迭代来生成不连续地址的序列。 直接存储器访问控制器可操作以执行数据传送，使得目的地数据格式与源数据格式不同。

公开(公告)号：US20060251092A1

公开(公告)日：2006-11-09

申请号：US11402192

申请日：2006-04-12

申请人： Johan Matterne ,  Martinus Wezelenburg

发明人： Johan Matterne ,  Martinus Wezelenburg

IPC分类号： H04L12/56

CPC分类号： G06F9/3877 ,  G06F9/3879

摘要： A data processing system is provided comprising a main processor operable to perform a plurality of data processing tasks, a data engine having a data engine core operable to perform a number of said plurality of data processing tasks on behalf of said main processor and a data stream processing unit providing a data communication path between said main processing unit and said data engine core. The data stream processing unit has a control interface operable to receive from said data engine core at least one command and a data stream controller operable to receive at least one input data stream and to perform at least one operation on said at least one input data stream to generate at least one output data stream comprising a sequence of data elements. The data stream processing unit is responsive to said at least one command from said data engine core to control said data stream controller to perform said at least one operation.

摘要翻译： 提供了一种数据处理系统，包括可操作以执行多个数据处理任务的主处理器，具有可操作以代表所述主处理器执行多个所述多个数据处理任务的数据引擎核心的数据引擎和数据流 处理单元，在所述主处理单元和所述数据引擎核心之间提供数据通信路径。 数据流处理单元具有可操作以从所述数据引擎核心接收至少一个命令的控制接口和可操作以接收至少一个输入数据流并且对所述至少一个输入数据流执行至少一个操作的数据流控制器 以产生包括数据元素序列的至少一个输出数据流。 数据流处理单元响应于来自所述数据引擎核心的所述至少一个命令来控制所述数据流控制器执行所述至少一个操作。

公开(公告)号：US20070028076A1

公开(公告)日：2007-02-01

申请号：US11189021

申请日：2005-07-26

申请人： Martinus Wezelenburg

发明人： Martinus Wezelenburg

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16

摘要： A data processing apparatus comprises data processing logic operable to perform data processing operations specified by program instructions. The data processing logic (140) has a plurality of functional units (142, 144, 146) configured to execute in parallel on data received from a data source. A decoder (130) is responsive to a single program instruction to control the data processing logic (140) to concurrently execute the single program instruction on each of a plurality of vector elements of each of a respective plurality of vector input operands (310, 320) received from the data source using the plurality of functional units (142, 144, 146). During execution of the single program instruction, the plurality of functional units (142, 144, 146) operate as a predetermined group on said plurality of vector elements (310, 320) to perform at least a matrix-vector calculation in which the matrix is a non-identity matrix and entries of the matrix are one of: (i) populated in dependence upon at least one of said vector elements of at least one of the plurality of vector input operands; and (ii) generated within said data processing logic as an explicit function of the single program instruction.

摘要翻译： 数据处理装置包括可操作以执行由程序指令指定的数据处理操作的数据处理逻辑。 数据处理逻辑（140）具有多个功能单元（142,144,146），被配置为并行地执行从数据源接收的数据。 解码器（130）响应于单个程序指令来控制数据处理逻辑（140），以在相应的多个向量输入操作数（310,320）中的每一个的多个向量元素中的每一个上同时执行单个程序指令 ）使用多个功能单元（142,144,146）从数据源接收。 在执行单个程序指令期间，多个功能单元（142,144,146）在所述多个向量元素（310,320）上作为预定组进行操作，以至少执行矩阵向量计算，其中矩阵为 非单位矩阵和矩阵的条目是以下之一：（i）根据多个矢量输入操作数中的至少一个的至少一个矢量元素填充; 和（ii）在所述数据处理逻辑内产生的单个程序指令的显式功能。

公开(公告)号：US20060253513A1

公开(公告)日：2006-11-09

申请号：US11201110

申请日：2005-08-11

申请人： Martinus Wezelenburg

发明人： Martinus Wezelenburg

IPC分类号： G06F17/14

CPC分类号： G06F17/142

摘要： A multi-dimensional FFT is calculated upon 2n rows of 2m data values set out end-to-end in memory by traversing the data set as a whole using stride values and block sizes which halve upon each pass through the data. As the data values represent multi-dimensional data, there are one or more dimensional boundaries within the data and as these are crossed the coefficient values being applied by the complex butterfly calculation are adjusted to take account of the manipulation being performed. The linearity of the matrix calculations underlying the butterfly calculation means that the order in which these calculations are performed is not significant and accordingly multiple passes with appropriate coefficient changes can perform a multi-dimensional calculation even if the different components of the calculation in respect of each dimension arise upon different passes through the data set.

摘要翻译： 通过使用步幅值遍历整个数据集，在存储器中端对端设置的2 数据值的2行行计算多维FFT 以及每次通过数据时减半的块大小。 当数据值表示多维数据时，在数据中存在一个或多个维度边界，并且由于这些被越过，所以通过复合蝶形计算所应用的系数值被调整以考虑正在执行的操作。 蝴蝶计算下的矩阵计算的线性意味着执行这些计算的顺序不重要，因此相应的具有适当系数变化的多次通过可以执行多维计算，即使每个计算的不同组成部分 尺寸出现在不同的通过数据集之后。

公开(公告)号：US20050227624A1

公开(公告)日：2005-10-13

申请号：US10999162

申请日：2004-11-29

申请人： Gerrit Hiddink ,  Amiram Levi ,  Harald Kampen ,  Martinus Wezelenburg

发明人： Gerrit Hiddink ,  Amiram Levi ,  Harald Kampen ,  Martinus Wezelenburg

IPC分类号： H04B17/00 ,  H04L12/56 ,  H04W36/30 ,  H04W72/08 ,  H04W84/18

CPC分类号： H04W36/30 ,  H04B17/382 ,  H04W72/08 ,  H04W84/18

摘要： Methods and apparatus are disclosed for automatically detecting when an operating channel needs to be changed in a wireless communication system. An alternate channel is selected by obtaining information about a plurality of available channels; assigning a score to each available channel; and selecting an alternate channel from the available channels based on the assigned score. The state of the selected alternate channel and the current channel are compared. A change to the selected alternate channel is initiated when one or more predefined criteria are satisfied.

摘要翻译： 公开了用于在无线通信系统中自动检测何时需要改变操作信道的方法和装置。 通过获得关于多个可用信道的信息来选择替代频道; 为每个可用频道分配乐谱; 并根据分配的分数从可用频道中选择一个备用频道。 比较所选替代频道和当前频道的状态。 当满足一个或多个预定义的标准时，启动对所选替代频道的改变。

公开(公告)号：US20070079297A1

公开(公告)日：2007-04-05

申请号：US11240798

申请日：2005-10-03

申请人： Martinus Wezelenburg ,  Koenraad Van Nieuwenhove

发明人： Martinus Wezelenburg ,  Koenraad Van Nieuwenhove

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A system and method for compiling a computer program, and software for performing such compilation, are provided, the compilation process determining where to store the computer program in memory for subsequent retrieval by a data processing apparatus that is to execute the computer program. The method can be used to compile a computer program for execution on the data processing apparatus having memory comprising a plurality of memory sections, each memory section having a record associated therewith identifying one or more access properties associated with that memory section. The method comprises the steps of: a) performing a compilation in order to generate an initial mapping of each code portion of the program in the memory; b) evaluating a cost function to generate a cost value associated with the initial mapping; c) if the cost value does not satisfy a threshold cost value, re-performing the compilation having regard to the record of each memory section in order to generate a modified mapping; d) re-evaluating the cost function to generate a revised cost value associated with the modified mapping; e) iteratively repeating steps (c) and (d) until a predetermined condition is met; and f) outputting the mapping whose associated cost value most closely satisfied the threshold cost value. Such an approach enables a reduction in the power consumption resulting from memory accesses, whilst also reducing local memory requirements. Further, it reduces the risk that the total size and complexity of the computer program will be strongly constrained by the given local program memory size without the need to resort to more expensive techniques such as caches and/or modular programming techniques.

摘要翻译： 提供了一种用于编译计算机程序的系统和方法以及用于执行这种编译的软件，编译过程确定将计算机程序存储在存储器中以便随后通过执行计算机程序的数据处理装置进行检索。 该方法可以用于编译计算机程序以在具有包括多个存储器部分的存储器的数据处理装置上执行，每个存储器部分具有与其相关联的记录，其中识别与该存储器部分相关联的一个或多个访问属性。 该方法包括以下步骤：a）执行编译以便产生存储器中程序的每个代码部分的初始映射; b）评估成本函数以生成与初始映射相关联的成本值; c）如果成本值不满足阈值成本值，则考虑到每个存储器部分的记录重新执行编译以便生成修改的映射; d）重新评估成本函数以产生与修改的映射相关联的修正成本值; e）迭代地重复步骤（c）和（d），直到满足预定条件; 以及f）输出其关联成本值最接近于阈值成本值的映射。 这种方法使得能够减少由存储器访问引起的功耗，同时还减少本地存储器要求。 此外，它降低了计算机程序的总体大小和复杂性将被给定的本地程序存储器大小强烈地限制的风险，而不需要采用诸如高速缓存和/或模块化编程技术的更昂贵的技术。