公开(公告)号：US11621923B2

公开(公告)日：2023-04-04

申请号：US17131403

申请日：2020-12-22

申请人： Marvell Asia Pte, Ltd.

发明人： Avinash Sodani ,  Enric Musoll ,  Dan Tu ,  Chia-Hsin Chen

IPC分类号： H04L12/863 ,  H04L47/62 ,  H04L49/9057 ,  H04L47/10 ,  H04L47/56

摘要： Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.

公开(公告)号：US11455575B1

公开(公告)日：2022-09-27

申请号：US16864031

申请日：2020-04-30

申请人： Marvell Asia Pte, Ltd. (Registration No. 199702379M)

发明人： Dan Tu ,  Enrique Musoll ,  Chia-Hsin Chen ,  Avinash Sodani

IPC分类号： G06N20/00 ,  G06F13/28 ,  G06F13/40

摘要： A multi-dimensional mesh architecture is proposed to support transmitting data packets from one source to a plurality of destinations in multicasting or broadcasting modes. Each data packet to be transmitted to the destinations carries a destination mask, wherein each bit in the destination mask represents a corresponding destination processing block in the mesh architecture the data packet is sent to. The data packet traverses through the mesh architecture based on a routing scheme, wherein the data packet first traverses in a first direction across a first set of processing blocks and then traverses in a second direction across a second set of processing blocks to the first destination. During the process, the data packet is only replicated when it reaches a splitting processing block where the paths to different destinations diverge. The original and the replicated data packets are then routed in different directions until they reach their respective destinations.