公开(公告)号：US12159648B1

公开(公告)日：2024-12-03

申请号：US18462915

申请日：2023-09-07

Applicant: Marvell Asia Pte Ltd

Inventor： Kok Hin Teng ,  Devrishi Khanna ,  Kai Wu ,  Sheung Yan Simon Ng

IPC: G11B20/10

Abstract: Write apparatus for a disk drive includes a write head, write current circuitry connected to the write head for generating a steady-state write current, overshoot current circuitry connected to the write head for generating write current overshoot pulses, and a T-coil termination network between (a) the write current circuitry and the overshoot current circuitry, and (b) a first node connected to a first input of a transmission line together with the write head. The T-coil termination network may include a first inductor connected to the first node, a second inductor coupled with the first inductor at a second node, and a first termination resistor between the first inductor and a common voltage. An output of the overshoot current circuitry may be connected to the first node, and an output of the write current circuitry may be connected to the second node.

公开(公告)号：US12142305B1

公开(公告)日：2024-11-12

申请号：US18467292

申请日：2023-09-14

Applicant: Marvell Asia Pte Ltd

Inventor： Kai Wu ,  Devrishi Khanna ,  Lei Mei

IPC: G11B5/00 ,  G11B5/02

Abstract: A data delay circuit, for delaying a portion of a data signal for application to a write head of a hard disk drive, includes a data delay cell including two inverters and a charge current source for charging at least one of the inverters, and a bias circuit for programming delay of the data delay cell. The bias circuit is in current-mirroring relationship with the charge current source and includes a current-based digital-to-analog converter (DAC) for programmably selecting the delay of the data delay cell, and a reference current source for the DAC. The data delay cell and the bias circuit are subject to gain error, and the data delay circuit further includes compensation circuitry for reducing the effect of the gain error. The compensation circuitry may include replica charge current and reference current sources that are fed back through a gain cell.

公开(公告)号：US11894025B1

公开(公告)日：2024-02-06

申请号：US18053470

申请日：2022-11-08

Applicant: Marvell Asia Pte Ltd

Inventor： Kai Wu ,  Mats Oberg ,  Hao Fang

IPC: G11B11/105 ,  G11B7/00 ,  G11B5/012 ,  G11B5/49

CPC classification number: G11B5/012 ,  G11B5/4946

Abstract: A method for writing data to a magnetic data storage medium includes detecting whether the duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold, and, when the duration, before the occurrence of the data transition, of the data to be written exceeds the predetermined threshold, writing the data by applying an initial pulse and then maintaining a steady-state write current for a defined interval, and when the duration, before the occurrence of the data transition, of the data to be written is at most equal to the predetermined threshold, writing the data by applying the initial pulse without applying a steady-state write current before the data transition. The predetermined threshold may be determined by size of a magnetic bubble formed when writing a single bit to the magnetic data storage medium. A subsequent pulse may be applied following the defined interval.

公开(公告)号：US11915729B1

公开(公告)日：2024-02-27

申请号：US18156852

申请日：2023-01-19

Applicant: Marvell Asia Pte Ltd

Inventor： Kai Wu ,  Hao Fang ,  Jorge Estuardo Licona

IPC: G11B20/10 ,  G11B11/105 ,  G11B5/09

CPC classification number: G11B5/09

Abstract: When writing data to a magnetic data storage medium, it is detected whether duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold. When the duration, before the transition, of the data to be written exceeds the predetermined threshold, the data is written by applying an initial pulse and then maintaining, until a shut-off pulse, a steady-state write current having an amplitude less than the initial pulse. A shut-off adjustment is determined based on a predetermined delay. The shut-off pulse is initiated at a time based on one bit period prior to the transition, adjusted by the shut-off adjustment. When the duration, before the transition, of the data to be written is at most equal to the predetermined threshold, the data is written by applying the initial pulse without applying a steady-state write current before the transition.