公开(公告)号：US08788729B1

公开(公告)日：2014-07-22

申请号：US13896869

申请日：2013-05-17

申请人： Marvell International Ltd.

发明人： Hongming Zheng ,  Gangadhar Gadepalli

IPC分类号： G06F3/00 ,  H04L12/56

CPC分类号： G06F5/12 ,  G06F3/0656 ,  G06F5/10

摘要： A system includes a memory that stores and outputs data in a first-in-first-out order. A sequence generator generates a sequence of first values, and randomly assigns the first values to blocks of the memory. A first memory module, based on the sequence of first values, accesses a first block of the memory. A conflict module, in response to a write or read conflict existing between the first and second memory modules due to the first memory module accessing the first block, resolves the write or read conflict. The conflict module resolves the write or read conflict by reading a value from the first block, and based on the value, either (i) causing the first memory module to write to a second block of the memory instead of the first block, or (ii) preventing the first memory module from reading from the first block.

摘要翻译： 系统包括以先进先出顺序存储和输出数据的存储器。 序列生成器生成第一个值的序列，并将第一个值随机分配给存储器的块。 第一存储器模块基于第一值序列访问存储器的第一块。 响应于由于第一存储器模块访问第一块而存在于第一和第二存储器模块之间的写入或读取冲突的冲突模块解决了写入或读取冲突。 冲突模块通过从第一块读取值并基于该值来解决写入或读取冲突，即（i）使得第一存储器模块写入存储器的第二块而不是第一块，或者（ ii）防止第一存储器模块从第一块读取。