公开(公告)号：US08729942B2

公开(公告)日：2014-05-20

申请号：US14085475

申请日：2013-11-20

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Mel Bazes

IPC: H03K3/00

CPC classification number: H03K3/00 ,  H03K3/0375 ,  H03K3/356173

Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.

Abstract translation: 本公开的一些实施例提供了一种D型触发器，包括：第一锁存器，被配置为基于输入信号的逻辑状态产生采样使能信号，并且基于所述第一锁存器的逻辑状态生成采样信号 输入信号和采样使能信号; 以及第二锁存器，被配置为响应于采样信号产生输出信号。 还描述和要求保护其他实施例。

公开(公告)号：US20140077853A1

公开(公告)日：2014-03-20

申请号：US14085475

申请日：2013-11-20

Applicant: Marvell Israel (M.I.S.L) Ltd.

Inventor： Mel Bazes

IPC: H03K3/00

CPC classification number: H03K3/00 ,  H03K3/0375 ,  H03K3/356173

Abstract: Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.

Abstract translation: 本公开的一些实施例提供了一种D型触发器，包括：第一锁存器，被配置为基于输入信号的逻辑状态产生采样使能信号，并且基于所述第一锁存器的逻辑状态生成采样信号 输入信号和采样使能信号; 以及第二锁存器，被配置为响应于采样信号产生输出信号。 还描述和要求保护其他实施例。