公开(公告)号：US20150215204A1

公开(公告)日：2015-07-30

申请号：US14679346

申请日：2015-04-06

Applicant: Marvell World Trade Ltd.

Inventor： Hakan Zeffer ,  Jakob Carlstrom ,  Par Westlund ,  Johan Back ,  Ronny Nilsson

IPC: H04L12/741 ,  H04L29/06 ,  H04L12/851

CPC classification number: H04L69/22 ,  H04L45/70 ,  H04L45/74 ,  H04L47/2441 ,  H04L67/10

Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.

Abstract translation: 所公开的实施例涉及为通信网络设备提供智能端口基础设施的系统。 这通过将高度可配置的预分类器模块并入端口基础设施来实现。 该预分类器使得可以重新分配分组数据以在分组的前面添加可配置的字节数，并且还从输入分组中选择感兴趣的数据用于进一步分析。 所选择的数据被发送到可配置的分类引擎中，其生成指定如何确定相关联的分组属性的指令。 然后基于指令生成分组属性，并且与分组一起被转发到下游处理单元。

公开(公告)号：US08995263B2

公开(公告)日：2015-03-31

申请号：US13898942

申请日：2013-05-21

Applicant: Marvell World Trade Ltd.

Inventor： Kurt Thomas Boden ,  Par Westlund

IPC: H04J1/16 ,  H04L12/28 ,  H04L12/861

CPC classification number: H04L49/9084 ,  H04L49/9078

Abstract: Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.

Abstract translation: 提供了系统和方法，用于对接收到的数据包的数量和包含在接收数据包中的字节数进行计数。 一种系统包括设置在集成电路中的第一存储器，所述第一存储器被配置为具有用于存储接收到的分组的小计的第一组位的第一组合计数器，以及用于存储包含在 收到的数据包。 第二个存储器是集成电路的外部。 第二存储器被配置为存储接收到的分组的总数和包含在接收分组中的总字节数。 更新电路被配置为当第一存储器中的第一组位或第二组位中的任何一个溢出时，更新存储在第二存储器中的分组的总数。

公开(公告)号：US10462267B2

公开(公告)日：2019-10-29

申请号：US15169011

申请日：2016-05-31

Applicant: Marvell World Trade Ltd.

Inventor： Hakan Zeffer ,  Jakob Carlstrom ,  Par Westlund ,  Johan Back ,  Ronny Nilsson

IPC: H04L12/28 ,  H04L29/06 ,  H04L12/851 ,  H04L12/741 ,  H04L12/721 ,  H04L29/08

Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.

公开(公告)号：US20160277549A1

公开(公告)日：2016-09-22

申请号：US15169011

申请日：2016-05-31

Applicant: Marvell World Trade Ltd.

Inventor： Hakan Zeffer ,  Jakob Carlstrom ,  Par Westlund ,  Johan Back ,  Ronny Nilsson

IPC: H04L29/06 ,  H04L12/721 ,  H04L29/08 ,  H04L12/851

CPC classification number: H04L69/22 ,  H04L45/70 ,  H04L45/74 ,  H04L47/2441 ,  H04L67/10

Abstract: The disclosed embodiments relate to a system that provides an intelligent port infrastructure for communication network devices. This is accomplished by incorporating a highly configurable pre-classifier module into the port infrastructure. This pre-classifier makes it possible to realign packet data to add a configurable number of bytes to the front of the packet, and also to select interesting data from incoming packets for further analysis. The selected data is sent into a configurable classification engine, which generates instructions that specify how to determine associated packet attributes. The packet attributes are then generated based on the instructions, and are forwarded along with the packet to downstream processing units.

公开(公告)号：US20130315259A1

公开(公告)日：2013-11-28

申请号：US13898942

申请日：2013-05-21

Applicant: Marvell World Trade Ltd.

Inventor： Kurt Thomas Boden ,  Par Westlund

IPC: H04L12/861

CPC classification number: H04L49/9084 ,  H04L49/9078

Abstract: Systems and methods are provided for counting a number of received packets and a number of bytes contained in the received packets. A system includes a first memory disposed in an integrated circuit, the first memory being configured as a first combination counter having a first set of bits for storing a subtotal of received packets, and a second set of bits for storing a subtotal of bytes contained in the received packets. A second memory is external to the integrated circuit. The second memory is configured to store a total number of received packets and a total number of bytes contained in the received packets. Update circuitry is configured to update the total number of packets stored in the second whenever either of the first set of bits or the second set of bits overflows in the first memory.

Abstract translation: 提供了系统和方法，用于对接收到的数据包的数量和包含在接收数据包中的字节数进行计数。 一种系统包括设置在集成电路中的第一存储器，所述第一存储器被配置为具有用于存储接收到的分组的小计的第一组位的第一组合计数器，以及用于存储包含在 收到的数据包。 第二个存储器是集成电路的外部。 第二存储器被配置为存储接收到的分组的总数和包含在接收分组中的总字节数。 更新电路被配置为当第一存储器中的第一组位或第二组位中的任何一个溢出时，更新存储在第二存储器中的分组的总数。