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公开(公告)号：US4493035A
公开(公告)日：1985-01-08
申请号：US447600
申请日：1982-12-07
CPC分类号： G06F9/3863 , G06F11/141
摘要： A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.
摘要翻译： 能够在指令执行期间检测到访问故障时能够自动地在外部存储器中存储与其内部状态相关的所有必要信息的数据处理器。 在纠正故障原因时，数据处理器根据检索的状态信息自动检索存储的状态信息并恢复其状态。 数据处理器然后恢复执行该指令。 可以在恢复指令执行时选择性地重新运行故障访问。 提供装置以验证所检索的状态信息是否有效。
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公开(公告)号：US4524415A
公开(公告)日：1985-06-18
申请号：US447721
申请日：1982-12-07
CPC分类号： G06F11/141 , G06F9/3824 , G06F9/3863
摘要： A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.
摘要翻译： 能够在指令执行期间检测到访问故障时能够自动地在外部存储器中存储与其内部状态相关的所有必要信息的数据处理器。 在纠正故障原因时，数据处理器根据检索的状态信息自动检索存储的状态信息并恢复其状态。 数据处理器然后恢复执行该指令。 可以在恢复指令执行时选择性地重新运行故障访问。 提供装置以验证所检索的状态信息是否有效。
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3.发明授权Microcoded processor executing microroutines with a user specified starting microaddress 失效微编码处理器用户指定启动微地址执行微程序
公开(公告)号：US4887203A
公开(公告)日：1989-12-12
申请号：US165409
申请日：1988-02-26
IPC分类号： G01R31/3185 , G06F9/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F9/226 , G01R31/318516
摘要： In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.
摘要翻译： 在微编码数据处理器中，提供使外部指定微机器的微地址的指令。 通过该指令，处理器可以被指示执行在正常执行期间不可用的特殊的微编码例程。 这些特殊的微编码例程可以执行有用的功能，例如以快速的方式测试处理器的电路的部分，否则将难以测试。 例如，诸如指令解码和控制可编程逻辑阵列（PLA）的常规结构的功能可以在将累积结果呈现给测试者之前直接门控到测试器或内部分析。 还可以有效地执行车载指令高速缓存以验证标签部分是否适当地确定“命中”和“未命中”，并且实际指令高速缓存部分准确地起作用。
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公开(公告)号：US4488228A
公开(公告)日：1984-12-11
申请号：US446801
申请日：1982-12-03
CPC分类号： G06F9/3863 , G06F11/141 , G06F9/3824
摘要： A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.
摘要翻译： 能够在指令执行期间检测到访问故障时能够自动地在外部存储器中存储与其内部状态相关的所有必要信息的数据处理器。 在纠正故障原因时，数据处理器根据检索的状态信息自动检索存储的状态信息并恢复其状态。 数据处理器然后恢复执行该指令。 可以在恢复指令执行时选择性地重新运行故障访问。 提供装置以验证所检索的状态信息是否有效。
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5.发明授权Method and apparatus for coordinating execution of an instruction by a coprocessor 失效用于协调由协处理器执行指令的方法和装置
公开(公告)号：US4729094A
公开(公告)日：1988-03-01
申请号：US30241
申请日：1987-03-24
CPC分类号： G06F9/3861 , G06F9/3881
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译： 使用标准总线周期将处理器与协处理器进行接口的系统。 处理器在其指令流中遇到具有特定操作字格式的指令时，将将操作字后的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。 在解码命令字后，协处理器将响应一组响应原语中的任何一个，这些响应原语定义了协处理器要求处理器在协处理器支持命令时执行的功能。 该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。
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公开(公告)号：US4649477A
公开(公告)日：1987-03-10
申请号：US749367
申请日：1985-06-27
CPC分类号： G06F9/30192 , G06F9/30036
摘要： A data processor having size selector in a controller for explicitly selecting the size of an operand independent of an instruction in an instruction register, together with means for selectively enabling the instruction register or other functional block, or a size selector to select the size of the operand. A size bus and a size multiplexer are also provided to route the size instructions. By using this size mechanism, the amount of sequencing and control logic is significantly reduced from prior data processors. The mechanism allows operations of different sizes to be performed during a single instruction while allowing instruction dependent sizing to be done residually.
摘要翻译： 一种在控制器中具有大小选择器的数据处理器，用于明确地选择独立于指令寄存器中的指令的操作数的大小，以及用于选择性地使能指令寄存器或其他功能块的装置，或者大小选择器选择尺寸选择器 操作数 还提供了尺寸总线和尺寸多路复用器来路由尺寸指令。 通过使用这种尺寸机制，排序和控制逻辑的数量从现有数据处理器显着减少。 该机制允许在单个指令期间执行不同大小的操作，同时允许依赖于指令的大小被完成。
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7.发明授权Method and apparatus for selectively evaluating an effective address for a coprocessor 失效用于选择性地评估协处理器的有效地址的方法和装置
公开(公告)号：US4811274A
公开(公告)日：1989-03-07
申请号：US95718
申请日：1987-09-14
CPC分类号： G06F9/3861 , G06F9/3881
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译： 使用标准总线周期将处理器与协处理器进行接口的系统。 处理器在其指令流中遇到具有特定操作字格式的指令时，将将操作字后的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。 在解码命令字后，协处理器将响应一组响应原语中的任何一个，这些响应原语定义了协处理器要求处理器在协处理器支持命令时执行的功能。 该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。
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8.发明授权Method and apparatus for selectively evaluating an effective address for a coprocessor 失效用于选择性地评估协处理器的有效地址的方法和装置
公开(公告)号：US4758978A
公开(公告)日：1988-07-19
申请号：US908912
申请日：1986-09-18
CPC分类号： G06F9/3881 , G06F9/3861
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译： 使用标准总线周期将处理器与协处理器进行接口的系统。 处理器在其指令流中遇到具有特定操作字格式的指令时，将将操作字后面的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。 在对命令字进行解码时，协处理器将响应一组响应原语中的任何一个，其定义协处理器要求处理器在协处理器支持命令时执行的功能。 该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。
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公开(公告)号：US4994961A
公开(公告)日：1991-02-19
申请号：US98441
申请日：1987-09-18
IPC分类号： G06F9/38
CPC分类号： G06F9/3881 , G06F9/3861
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
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10.发明授权Method and apparatus for executing an instruction contingent upon a condition present in another data processor 失效用于根据存在于另一数据处理器中的条件执行指令的方法和装置
公开(公告)号：US4750110A
公开(公告)日：1988-06-07
申请号：US485671
申请日：1983-04-18
CPC分类号： G06F9/3877 , G06F9/3861
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译： 使用标准总线周期将处理器与协处理器进行接口的系统。 处理器在其指令流中遇到具有特定操作字格式的指令时，将将运行字之后的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。 在对命令字进行解码时，协处理器将响应一组响应原语中的任何一个，其定义协处理器要求处理器在协处理器支持命令时执行的功能。 该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。
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