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公开(公告)号：US20120325990A1
公开(公告)日：2012-12-27
申请号：US13575514
申请日：2011-01-26
CPC分类号： B60T7/06 , B21D35/001 , B21D53/88 , G05G1/30 , Y10T74/20888 , Y10T74/20912
摘要： The invention is characterized in that, when protrusion parts 30 are raised from a substrate W and the protrusion parts 30 are formed into spacers 12 with a predetermined outer diameter D and height H, the protrusion parts 30 are temporarily formed so as to have a diameter larger than a predetermined outer diameter D and a height larger than a predetermined height H, and the protrusion parts 30 are crushed, and leading end portions 30b of the protrusion parts 30 are protruded in a radially outward direction so as to have a double-layered structure, and then through-holes 35 are opened at the leading end portions 30b. Accordingly, the leading end portions 30b have strength due to a double-layered structure, and side portions 30a also have high strength due to contraction by pressing, whereby the sleeve-integrated member includes the entirely high-strength spacers 12.
摘要翻译： 本发明的特征在于，当突出部30从基板W升起并且突出部30形成为具有预定外径D和高度H的间隔件12时，突出部30被暂时形成为具有直径 大于预定的外径D和大于预定高度H的高度，并且突出部30被压扁，并且突出部30的前端部30b沿径向向外的方向突出以具有双层 结构，然后在前端部30b开通通孔35。 因此，前端部30b由于双层结构而具有强度，并且侧部30a也由于按压而收缩而具有高强度，由此套筒一体化构件包括完全高强度的间隔件12。
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公开(公告)号：US08863614B2
公开(公告)日：2014-10-21
申请号：US13575514
申请日：2011-01-26
CPC分类号： B60T7/06 , B21D35/001 , B21D53/88 , G05G1/30 , Y10T74/20888 , Y10T74/20912
摘要： The invention is characterized in that, when protrusion parts 30 are raised from a substrate W and the protrusion parts 30 are formed into spacers 12 with a predetermined outer diameter D and height H, the protrusion parts 30 are temporarily formed so as to have a diameter larger than a predetermined outer diameter D and a height larger than a predetermined height H, and the protrusion parts 30 are crushed, and leading end portions 30b of the protrusion parts 30 are protruded in a radially outward direction so as to have a double-layered structure, and then through-holes 35 are opened at the leading end portions 30b. Accordingly, the leading end portions 30b have strength due to a double-layered structure, and side portions 30a also have high strength due to contraction by pressing, whereby the sleeve-integrated member includes the entirely high-strength spacers 12.
摘要翻译： 本发明的特征在于，当突出部30从基板W升起并且突出部30形成为具有预定外径D和高度H的间隔件12时，突出部30被暂时形成为具有直径 大于预定的外径D和大于预定高度H的高度，并且突出部30被压扁，并且突出部30的前端部30b沿径向向外的方向突出，以具有双层 结构，然后在前端部30b开通通孔35。 因此，前端部30b由于双层结构而具有强度，并且侧部30a也由于按压而收缩而具有高强度，由此套筒一体化构件包括完全高强度的间隔件12。
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公开(公告)号：US5321666A
公开(公告)日：1994-06-14
申请号：US716821
申请日：1991-06-17
申请人： Hidetada Fukunaka , Akira Ishiyama
发明人： Hidetada Fukunaka , Akira Ishiyama
IPC分类号： G11C11/409 , G11C7/10 , G11C7/22 , G11C8/18 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1078 , G11C8/18
摘要： A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.
摘要翻译： 包括动态随机存取存储器的存储器系统的控制电路可以包括形成在公共衬底上的第一集成电路。 第一集成电路可以包括响应于外部存储器访问请求信号的电路，用于产生用于控制动态随机存取存储器的操作定时的控制信号，以将控制信号提供给动态随机存取存储器和用于产生地址的电路 信号，用于指定要访问的动态随机存取存储器的地址以将地址信号提供给动态随机存取存储器。 第二集成电路包括用于从动态随机存取存储器读取数据并用于在动态随机存取存储器中写入数据的读/写电路。
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公开(公告)号：US5584004A
公开(公告)日：1996-12-10
申请号：US855091
申请日：1992-03-20
CPC分类号： G06F12/0692
摘要： A data processing system is provided which includes a plurality of subsystems each including at least one instruction processor, at least one input/output device and at least one main storage device connected by local bus. The subsystems are connected to one another through bus extenders and inter-subsystem transfer lines. Each of the main storage devices is assigned for a partial address space as a part of the system address space. When an instruction processor or an input/output processor on each of the subsystems makes access to a main storage device, the operation of the system is as follows. If the address of access is in the address space limit of a main storage device on an inner subsystem, access to the main storage device on the inner subsystem is made. If the address of access is out of the address space limit of the main storage device on the inner subsystem and in the system address space assigned to the system, access to a main storage device on one of outer subsystems is made through a bus extender on the inner subsystem, inter-subsystem transfer lines and another bus extender on the one outer subsystems.
摘要翻译： 提供了一种数据处理系统，其包括多个子系统，每个子系统包括至少一个指令处理器，至少一个输入/输出设备以及通过本地总线连接的至少一个主存储设备。 子系统通过总线扩展器和子系统间传输线相互连接。 每个主存储设备被分配为部分地址空间作为系统地址空间的一部分。 当每个子系统上的指令处理器或输入/输出处理器访问主存储设备时，系统的操作如下。 如果访问地址在内部子系统上的主存储设备的地址空间限制内，则进入内部子系统上的主存储设备。 如果访问地址超出内部子系统上的主存储设备的地址空间限制，以及分配给系统的系统地址空间，则通过总线扩展器访问外部子系统之一的主存储设备 内部子系统，子系统间传输线路和一个外部子系统上的另一个总线扩展器。
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公开(公告)号：USRE35978E
公开(公告)日：1998-12-01
申请号：US660977
申请日：1996-06-12
申请人： Hidetada Fukunaka , Akira Ishiyama
发明人： Hidetada Fukunaka , Akira Ishiyama
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1078 , G11C8/18
摘要： A control circuit of a memory system including a dynamic random access memory may include a first integrated circuit formed on a common substrate. The first integrated circuit may include a circuit responsive to an external memory access request signal for generating a control signal for controlling an operation timing of the dynamic random access memory to supply the control signal to the dynamic random access memory and a circuit for generating an address signal for specifying an address of the dynamic random access memory to be accessed to supply the address signal to the dynamic random access memory. A second integrated circuit includes a read/write circuit for reading data from the dynamic random access memory and for writing data in the dynamic random access memory.
摘要翻译： 包括动态随机存取存储器的存储器系统的控制电路可以包括形成在公共衬底上的第一集成电路。 第一集成电路可以包括响应于外部存储器访问请求信号的电路，用于产生用于控制动态随机存取存储器的操作定时的控制信号，以将控制信号提供给动态随机存取存储器和用于产生地址的电路 信号，用于指定要访问的动态随机存取存储器的地址以将地址信号提供给动态随机存取存储器。 第二集成电路包括用于从动态随机存取存储器读取数据并用于在动态随机存取存储器中写入数据的读/写电路。
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6.发明授权Method and apparatus for transferring addresses and information in a buffer memory and a common main storage device 失效用于在缓冲存储器和公共主存储装置中传送地址和信息的方法和装置
公开(公告)号：US5008817A
公开(公告)日：1991-04-16
申请号：US222841
申请日：1988-07-22
IPC分类号： G06F15/16 , G06F12/08 , G06F15/167 , G06F15/177
CPC分类号： G06F12/0831
摘要： Provided is an information processing apparatus in which at least two processing units each having a buffer memory are mutually connected to each other and to a main storage unit through a bus. All of the processing units having the buffer memories continuously monitor the state of the bus. When one of the processing units generates an information updating request in order to update the storage content of the main storage unit, the other processing units read a memory address from the bus. The memory address corresponds to the information to be updated, and is sent to the main storage unit through the bus together with the information updating request. The memory address is compared with memory addresses contained in the buffer memory of the other processing units. If there is a coincidence, information in the relevant memory address exists in its own buffer memory. Thereafter this information is invalidated.
摘要翻译： 提供了一种信息处理装置，其中至少两个具有缓冲存储器的处理单元彼此相互连接并通过总线相互连接到主存储单元。 具有缓冲存储器的所有处理单元连续地监视总线的状态。 当其中一个处理单元产生信息更新请求以更新主存储单元的存储内容时，其他处理单元从总线读取存储器地址。 存储器地址对应于要更新的信息，并且与信息更新请求一起通过总线发送到主存储单元。 将存储器地址与包含在其他处理单元的缓冲存储器中的存储器地址进行比较。 如果存在巧合，相关存储器地址中的信息存在于其自身的缓冲存储器中。 此后，此信息无效。
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