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公开(公告)号：US11860813B2
公开(公告)日：2024-01-02
申请号：US17483641
申请日：2021-09-23
申请人： Rambus Inc.
发明人： Keith Lowery , Vlad Fruchter
IPC分类号： G06F15/173 , G06F12/06 , G06F3/06 , G06F13/16 , H04L67/1097 , H04L67/568
CPC分类号： G06F15/17331 , G06F3/0619 , G06F12/0653 , G06F12/0692 , G06F13/16 , H04L67/1097 , H04L67/568
摘要： A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to said memory unit controller. The memory related command is translated by the processor into a plurality of commands that are formatted to perform prescribed data manipulation operations on data of the plurality of memory devices stored in data structures. The plurality of primitive commands is executed on data stored in the memory devices to produce a result, wherein the executing is performed by the memory unit controller. A direct memory transfer of the result is established over the communication protocol to a network.
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2.发明授权公开(公告)号：US11687612B2
公开(公告)日：2023-06-27
申请号：US17531530
申请日：2021-11-19
申请人： Intuit Inc.
发明人： Elik Sror , Oren Sar Shalom , Rami Cohen
IPC分类号： G06F16/957 , G06F17/16 , G06N3/08 , G06F12/06 , G06F12/02 , G06F12/0895
CPC分类号： G06F16/9574 , G06F17/16 , G06N3/08 , G06F12/0238 , G06F12/0692 , G06F12/0895
摘要： A method for mitigating cold starts in recommendations includes receiving a request that identifies a requested page and identifying a content vector of the requested page. The content vector is generated based on providing text of the requested page to a neural network text encoder. The method further includes selecting, based on the content vector, a link to a cold start page that does not satisfy a threshold level of interaction data. The selected link is ranked above a second link to a warm page that does satisfy the threshold level of the interaction data. The method further includes presenting the requested page with the selected link.
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公开(公告)号：US20180150256A1
公开(公告)日：2018-05-31
申请号：US15716790
申请日：2017-09-27
申请人： Intel Corporation
IPC分类号： G06F3/06
CPC分类号： G06F3/0641 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/4881 , G06F9/5038 , G06F9/505 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/1453 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3409 , G06F12/023 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F15/80 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/046 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L41/12 , H04L41/142 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L47/78 , H04L49/104 , H04L61/2007 , H04L63/1425 , H04L67/10 , H04L67/1014 , H04L67/327 , H04L67/36 , H05K7/1452 , H05K7/1487
摘要： Technologies for providing data deduplication in a disaggregated architecture include a network device. The network device is to receive, from a compute sled, a request to write a data block to one or more data storage sleds and determine, for each of one or more data sub-blocks within the data block and from deduplication data indicative of physical addresses of data sub-blocks, whether each data sub-block is already stored in a data storage device of a data storage sled. Additionally, the network device is to write, in the deduplication data and in response to a determination that a data sub-block is already stored in a data storage device, a pointer to a physical address of the already-stored data sub-block in association with a logical address of the data sub-block.
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公开(公告)号：US20170249996A1
公开(公告)日：2017-08-31
申请号：US15055466
申请日：2016-02-26
发明人： Mark W. Gottscho , Mohammed Shoaib , Sriram Govindan , Mark Santaniello , Bikash Sharma , J. Michael Andrewartha , Jie Liu , Badriddine Khessib
CPC分类号： G11C29/38 , G06F9/5016 , G06F11/3037 , G06F11/34 , G06F11/3419 , G06F11/3428 , G06F11/3433 , G06F12/0646 , G06F12/0692 , G11C29/44
摘要： Technology relating to tuning for operating memory devices is disclosed. The technology includes a computing device that selectively configures operating parameters for at least one operating memory device based at least in part of performance characteristics for an application or other workload that the computing device has been requested to execute. This technology may be implemented, at least in part, in the firmware via a Basic Input/Output System (BIOS) or Unified Extensible Firmware Interface (UEFI) of the computing device. Further, this technology may be employed by a computing device that is executing workloads on behalf of a distributed computing system, e.g., in a data center. Such data centers may include, for example, thousands of computing devices and even more operating memory devices.
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公开(公告)号：US09727478B2
公开(公告)日：2017-08-08
申请号：US15209085
申请日：2016-07-13
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G06F13/12 , G06F12/0875 , G11C17/16 , G06F3/06 , G06F9/44 , G06F9/445 , G06F12/06 , G06F12/0806 , G11C17/18 , G11C29/00 , G06F11/10 , G06F12/0802 , G11C29/52 , G06F12/128 , G06F1/24 , G06F12/084 , G06F12/0811
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.
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公开(公告)号：US09652395B2
公开(公告)日：2017-05-16
申请号：US14707299
申请日：2015-05-08
发明人： John Carl Mese , Arnold S. Weksler , Rod D. Waltermann , Nathan J. Peterson , Russell Speight VanBlon
IPC分类号： G06F12/00 , G06F12/0862 , G06F12/123 , G06F12/06
CPC分类号： G06F12/0862 , G06F3/06 , G06F9/50 , G06F12/0692 , G06F12/123
摘要： In one aspect, a device includes a processor, memory accessible to the processor, and storage accessible to the processor. The storage bears instructions executable by the processor to determine a context associated with the device and at least in part based on the determination, configure a standby portion of the memory.
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公开(公告)号：US09588887B2
公开(公告)日：2017-03-07
申请号：US13973416
申请日：2013-08-22
CPC分类号： G06F12/0692 , G11B20/10527 , G11B20/1252 , G11C7/10 , G11C7/1012
摘要： A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.
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公开(公告)号：US09588886B2
公开(公告)日：2017-03-07
申请号：US13839132
申请日：2013-03-15
CPC分类号： G06F12/0692 , G11B20/10527 , G11B20/1252 , G11C7/10 , G11C7/1012
摘要： A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.
摘要翻译： 数据存储系统包括数据存储和随机存取存储器。 排序模块通信地耦合到随机存取存储器，并且被配置为对在随机存取存储器中接收的输入写入数据的数据块进行排序。 存储控制器通信地耦合到随机存取存储器和数据存储器，并且被配置为将排序的数据块作为单独排序的数据块集写入数据存储器的暂存区域。 一种方法和处理器实现的过程提供对在数据存储器的随机存取存储器中接收的输入写入数据的数据块进行排序，并将排序的数据块作为单独排序的数据块集合写入数据存储器的暂存区域。
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公开(公告)号：US20150178103A1
公开(公告)日：2015-06-25
申请号：US14635006
申请日：2015-03-02
发明人： G. GLENN HENRY , DINESH K. JAIN
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.
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10.发明授权Chipset support for binding and migrating hardware devices among heterogeneous processing units 有权芯片组支持在异构处理单元之间绑定和迁移硬件设备公开(公告)号：US09032101B1
公开(公告)日：2015-05-12
申请号：US12332009
申请日：2008-12-10
申请人： Michael Brian Cox , Brad W. Simeral
发明人： Michael Brian Cox , Brad W. Simeral
CPC分类号： G06F12/1081 , G06F12/0292 , G06F12/0692 , G06F2212/206
摘要： A method for providing access to hardware devices by a processor without causing conflicts with other processors included in a computer system. The method includes receiving a first address map from a first processor and a second address map from a second processor, where each address map includes memory-mapped input/output (I/O) apertures for a set of hardware devices that the processor is configured to access. The method further includes generating a global address map by combining the first address map and the second address map, receiving a first access request from the first processor and routing the first access request to a hardware device based on an address mapping included in the global address map. Advantageously, heterogeneous processors included in multi-processor system can access any hardware device included in the computer system, without modifying the processors, one or more operating systems executed by each processor, or the hardware devices.
摘要翻译： 一种用于通过处理器提供对硬件设备的访问的方法，而不引起与计算机系统中包括的其他处理器的冲突。 该方法包括从第一处理器接收第一地址映射和从第二处理器接收第二地址映射，其中每个地址映射包括处理器配置的一组硬件设备的存储器映射的输入/输出（I / O）孔径 访问。 该方法还包括通过组合第一地址映射和第二地址映射来生成全局地址映射，从第一处理器接收第一访问请求，并基于包含在全局地址中的地址映射将第一访问请求路由到硬件设备 地图。 有利地，包括在多处理器系统中的异构处理器可以访问包括在计算机系统中的任何硬件设备，而无需修改处理器，由每个处理器执行的一个或多个操作系统或硬件设备。
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