公开(公告)号：US20110032414A1

公开(公告)日：2011-02-10

申请号：US12797740

申请日：2010-06-10

申请人： Masato Sumiyoshi ,  Nau Ozaki ,  Masashi Jobashi

发明人： Masato Sumiyoshi ,  Nau Ozaki ,  Masashi Jobashi

IPC分类号： H04N5/238

CPC分类号： H04N5/2353 ,  H04N5/144

摘要： A digital camera that is an image pickup device includes: a sensor; a background portion movement speed calculating unit configured to calculate a movement speed of a background portion of a subject from a plurality of images picked up by the sensor; and a shutter speed calculating unit configured to calculate a shutter speed from the movement speed and a predetermined image flow quantity.

摘要翻译： 作为图像拾取装置的数字照相机包括：传感器; 背景部分移动速度计算单元，被配置为从由所述传感器拾取的多个图像中计算被摄体的背景部分的移动速度; 以及快门速度计算单元，被配置为根据移动速度和预定图像流量来计算快门速度。

公开(公告)号：US20080238733A1

公开(公告)日：2008-10-02

申请号：US12041395

申请日：2008-03-03

申请人： Tatsuhiro SUZUMURA ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

发明人： Tatsuhiro SUZUMURA ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/42

CPC分类号： H03M7/40 ,  H03M7/42 ,  H04N19/13

摘要： According to the present invention, there is provided an image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and update the suffix length suffixLength.

摘要翻译： 根据本发明，提供了一种图像解码装置，具有：表选择控制器，被配置为输出选择前缀level_prefix，后缀level_suffix和TrailingOnes语法之一的语法选择信号; 配置为接收比特流，语法选择信号和后缀长度suffixLength的可变长度码解码装置，并且通过使用包含在比特流和后缀长度suffixLength中的数据，同时解码前缀level_prefix和后缀level_suffix 并且如果语法选择信号选择前缀level_prefix和后缀level_suffix，并且如果语法选择信号选择TrailingOnes语法则解码TrailingOnes语法并输出结果，则输出结果; 电平形成装置，被配置为接收解码的前缀电平_prefix，解码的后缀电平补码和解码的TrailingOnes语法，并且形成并输出电平; 以及后缀长度更新装置，被配置为接收解码的前缀级别_refref，解码的后缀level_suffix和解码的TrailingOnes语法，并更新后缀长度suffixLength。

公开(公告)号：US20090097567A1

公开(公告)日：2009-04-16

申请号：US12245984

申请日：2008-10-06

申请人： Yoshinori Shigeta ,  Hiromitsu Nakayama ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Tatsuhiro Suzumura ,  Takaya Ogawa ,  Masashi Jobashi

发明人： Yoshinori Shigeta ,  Hiromitsu Nakayama ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Tatsuhiro Suzumura ,  Takaya Ogawa ,  Masashi Jobashi

IPC分类号： H04N7/12

CPC分类号： H04N19/90 ,  H04N19/12 ,  H04N19/13 ,  H04N19/176 ,  H04N19/61

摘要： An encoding apparatus includes: an orthogonal transformation unit configured to orthogonally transform image data of a predetermined block size; a binarization unit configured to binarize the image data outputted from the orthogonal transformation unit; an arithmetic encoding unit configured to arithmetically encode the binary data generated by the binarization unit; and a prediction unit configured to predict, from the binary data, whether or not the amount of arithmetically encoded data generated by the arithmetic encoding unit exceeds a permissible maximum code amount based on a predetermined encoding standard. The encoding apparatus performs, when the prediction result is that the amount of arithmetically encoded data exceeds the maximum code amount, control to prevent the arithmetic encoding by the arithmetic encoding unit from being performed to the binary data corresponding to the prediction result.

摘要翻译： 编码装置包括：正交变换单元，被配置为对预定块大小的图像数据进行正交变换; 二值化单元，被配置为二进制化从正交变换单元输出的图像数据; 算术编码单元，被配置为对由二值化单元生成的二进制数据进行算术编码; 以及预测单元，被配置为从二进制数据预测由算术编码单元生成的算术编码数据的量是否超过基于预定编码标准的允许最大代码量。 当预测结果是算术编码数据的量超过最大代码量时，编码装置执行防止由算术编码单元进行的算术编码对与预测结果相对应的二进制数据的控制。

公开(公告)号：US07586426B2

公开(公告)日：2009-09-08

申请号：US12123793

申请日：2008-05-20

申请人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

发明人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/00

CPC分类号： H04N19/42 ,  H04N19/13

摘要： An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

摘要翻译： 图像编码装置包括可变长度编码部分，算术编码部分和公共缓冲存储器。 可变长度编码部分输入图像数据并输出应用可变长度编码的二进制码序列。 算术编码部分对从可变长度编码部分输出的二进制码序列进行算术编码。 公共缓冲存储器在可变长度编码部分和算术编码部分之间发送和接收数据。

公开(公告)号：US20080291062A1

公开(公告)日：2008-11-27

申请号：US12123793

申请日：2008-05-20

申请人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

发明人： Kiwamu Watanabe ,  Shuji Michinaka ,  Tatsuhiro Suzumura ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Satoshi Takekawa ,  Masashi Jobashi ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/34 ,  G06K9/36

CPC分类号： H04N19/42 ,  H04N19/13

摘要： An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.

摘要翻译： 图像编码装置包括可变长度编码部分，算术编码部分和公共缓冲存储器。 可变长度编码部分输入图像数据并输出应用可变长度编码的二进制码序列。 算术编码部分对从可变长度编码部分输出的二进制码序列进行算术编码。 公共缓冲存储器在可变长度编码部分和算术编码部分之间发送和接收数据。

公开(公告)号：US08155204B2

公开(公告)日：2012-04-10

申请号：US11857874

申请日：2007-09-19

申请人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Masashi Jobashi ,  Takaya Ogawa ,  Hiromitsu Nakayama ,  Satoshi Takekawa ,  Yoshinori Shigeta ,  Akihiro Oue

发明人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Masashi Jobashi ,  Takaya Ogawa ,  Hiromitsu Nakayama ,  Satoshi Takekawa ,  Yoshinori Shigeta ,  Akihiro Oue

IPC分类号： H04N11/02

CPC分类号： H04N19/423 ,  H04N19/105 ,  H04N19/112 ,  H04N19/44 ,  H04N19/61

摘要： The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.

摘要翻译： 根据本发明的一个方面的图像解码装置和图像解码方法具有将过去被解码为图像的图像作为参考图像存储到帧存储器中的结构，其中参考图像中的顶行是 存储在顶部区域中，参考图像中的底线存储在底部区域中，以便使用过去解码的图像的一部分作为当前解码的图像中的参考块; 并且将参考图像中的最上面的最上面的行或最上面的行选择性地复制并存储在帧存储器中的顶部区域和底部区域中的参考图像中的最上面的顶部行和最上面的底部的区域，并且选择性地复印 并且将参考图像中的最下顶行或最下底行存储在帧存储器中的顶区域和底区中的参考图片中的最下顶行和最​​下底行下方的区域。

公开(公告)号：US07602319B2

公开(公告)日：2009-10-13

申请号：US12041395

申请日：2008-03-03

申请人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

发明人： Tatsuhiro Suzumura ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/40

CPC分类号： H03M7/40 ,  H03M7/42 ,  H04N19/13

摘要： An image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix, a suffix, and a syntax; a variable length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length, and, by using data contained in the bit stream and the suffix length, simultaneously decode the prefix and the suffix and output the result if the syntax selection signal selects the prefix 1 and the suffix, and decode the syntax and output the result if the syntax selection signal selects the syntax; a level formation device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and update the suffix length.

摘要翻译： 一种图像解码装置，具有：表选择控制器，被配置为输出选择前缀，后缀和语法之一的语法选择信号; 被配置为接收比特流，语法选择信号和后缀长度的可变长度码解码装置，并且通过使用包含在比特流和后缀长度中的数据同时解码前缀和后缀并输出结果，如果 语法选择信号选择前缀1和后缀，并且如果语法选择信号选择语法，则对语法进行解码并输出结果; 电平形成装置，被配置为接收解码前缀，解码后缀和解码语法，并形成并输出电平; 以及后缀长度更新装置，被配置为接收解码的前缀，解码的后缀和解码的语法，并更新后缀长度。

公开(公告)号：US07567189B2

公开(公告)日：2009-07-28

申请号：US12027637

申请日：2008-02-07

申请人： Takaya Ogawa ,  Masashi Jobashi ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Satoshi Takekawa ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Akihiro Oue ,  Shuji Michinaka

发明人： Takaya Ogawa ,  Masashi Jobashi ,  Kiwamu Watanabe ,  Tatsuhiro Suzumura ,  Satoshi Takekawa ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Akihiro Oue ,  Shuji Michinaka

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced. A variable length code decoding apparatus includes an input unit which receives variable length coding data, a plurality of FIFO memories which store the variable length coding data and output or update the variable length coding data on the basis of a codeword length of the variable length coding data, a FIFO input selecting unit which outputs the variable length coding data to one of the plurality of FIFO memories, a variable length coding table storing unit which stores a variable length coding table representing a relationship between the variable length coding data, the codeword length and a decoding value, reads the variable length coding data stored in one of the plurality of FIFO memories, and compares the read variable length coding data with the variable length coding table, a table selecting unit which determines the codeword length and the decoding value on the basis of a comparison result of the variable length coding table storing unit, and outputs the determined codeword length to one of the plurality of FIFO memories, and a control unit which selects one of the plurality of FIFO memories as a destination FIFO memory, reads the variable length coding data from the input unit or one of the unselected FIFO memories, and controls the FIFO input selecting unit such that the read variable length coding data is output to the selected FIFO memory.

摘要翻译： 当使用多个FIFO存储器和可变长度编码表之间的组合时，当输出码字长度时，由可变长度编码表输出的作为输出目的地的FIFO存储器的数量增加而产生的负载 降低了。 可变长度码解码装置包括接收可变长度编码数据的输入单元，存储可变长度编码数据的多个FIFO存储器，并且根据可变长度编码数据的码字长度输出或更新可变长度编码数据 数据，FIFO输入选择单元，其向多个FIFO存储器之一输出可变长度编码数据;可变长度编码表存储单元，其存储表示可变长度编码数据，码字长度之间的关系的可变长度编码表 和解码值，读取存储在多个FIFO存储器之一中的可变长度编码数据，并将读取的可变长度编码数据与可变长度编码表进行比较，确定代码字长度和解码值的表格选择单元 是可变长度编码表存储单元的比较结果的基础，并输出确定的码字 长度到多个FIFO存储器中的一个，以及选择多个FIFO存储器之一作为目的地FIFO存储器的控制单元，从输入单元或未选择的FIFO存储器之一读取可变长度编码数据，并且控制 FIFO输入选择单元，使得读取的可变长度编码数据被输出到所选择的FIFO存储器。

公开(公告)号：US08477051B2

公开(公告)日：2013-07-02

申请号：US13424205

申请日：2012-03-19

申请人： Kojiro Suzuki ,  Masashi Jobashi

发明人： Kojiro Suzuki ,  Masashi Jobashi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： A variable-length code decoding apparatus has a first-table storing part to store a first table, a second-table storing part to store a second table, a priority determining part to read out by priority a combination of zero information that is stored in the second table and corresponds a combination of variable-length codes having the largest number of codes, whereas if variable-length codes included in the input bitstream is not stored in the second table but stored in the first table, to read out zero information, and a decoding part to generate the decoded data based on the zero information or the combination of zero information read out by the priority determining part.

摘要翻译： 可变长码解码装置具有存储第一表的第一表存储部，存储第二表的第二表存储部，优先权确定部，优先读出存储在 第二表并且对应于具有最大代码数的可变长度代码的组合，而如果包括在输入比特流中的可变长度代码未被存储在第二表中但存储在第一表中，则读出零信息， 以及解码部分，用于基于优先级确定部分读出的零信息或零信息的组合来生成解码数据。

公开(公告)号：US20120306669A1

公开(公告)日：2012-12-06

申请号：US13424205

申请日：2012-03-19

申请人： Kojiro Suzuki ,  Masashi Jobashi

发明人： Kojiro Suzuki ,  Masashi Jobashi

IPC分类号： H03M7/40

CPC分类号： H03M7/40

摘要： A variable-length code decoding apparatus has a first-table storing part to store a first table, a second-table storing part to store a second table, a priority determining part to read out by priority a combination of zero information that is stored in the second table and corresponds a combination of variable-length codes having the largest number of codes, whereas if variable-length codes included in the input bitstream is not stored in the second table but stored in the first table, to read out zero information, and a decoding part to generate the decoded data based on the zero information or the combination of zero information read out by the priority determining part.

摘要翻译： 可变长码解码装置具有存储第一表的第一表存储部，存储第二表的第二表存储部，优先权确定部，优先读出存储在 第二表并且对应于具有最大代码数的可变长度代码的组合，而如果包括在输入比特流中的可变长度代码未被存储在第二表中但存储在第一表中，则读出零信息， 以及解码部分，用于基于优先级确定部分读出的零信息或零信息的组合来生成解码数据。