公开(公告)号：US20090129303A1

公开(公告)日：2009-05-21

申请号：US12199298

申请日：2008-08-27

申请人： Masato TOMITA ,  Takashi SHIMIZU ,  Hideaki WATANABE

发明人： Masato TOMITA ,  Takashi SHIMIZU ,  Hideaki WATANABE

IPC分类号： G08C17/00

CPC分类号： H04L25/0264 ,  H03K5/08 ,  H04L25/0272 ,  H04L25/028

摘要： A data transmission circuit transmitting an activation signal prior to a data signal through a signal transmission line, including: an activation detection signal generation unit for generating an activation detection signal by detecting the activation signal; and a wakeup signal generation unit for being activated by the activation detection signal, and generating a wakeup signal by detecting that the activation signal is transmitted for a predetermined time.

摘要翻译： 数据传输电路通过信号传输线在数据信号之前传输激活信号，包括：激活检测信号产生单元，用于通过检测激活信号产生激活检测信号; 以及唤醒信号生成单元，用于由激活检测信号激活，并且通过检测到激活信号在预定时间内发送来产生唤醒信号。

公开(公告)号：US20130287154A1

公开(公告)日：2013-10-31

申请号：US13927831

申请日：2013-06-26

申请人： Masato TOMITA

发明人： Masato TOMITA

IPC分类号： H04L7/04

CPC分类号： H04L7/04 ,  G06F1/12 ,  H03L7/095 ,  H03L7/107 ,  H03L7/1075 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0083 ,  H04L7/033

摘要： A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

摘要翻译： 一种用于防止CDR电路中的缺陷妨碍连接节点之间的同步并防止连接故障的方法和装置。 CDR电路从接收的数据生成同步时钟。 当从接收到接收到的数据的接收开始的第一预定时间过去时，连接失败处理器执行连接失败处理，如果在连接节点之间的同步时钟不建立，则连接失败处理器执行连接失败处理。 如果当从接收到的数据的接收开始的时间比第一预定时间短的第二预定时间过去时，校正处理器校正了基于连接节点之间的同步时钟的同步的CDR电路的操作。

公开(公告)号：US20110216863A1

公开(公告)日：2011-09-08

申请号：US13022992

申请日：2011-02-08

申请人： Masato TOMITA ,  Hideaki WATANABE

发明人： Masato TOMITA ,  Hideaki WATANABE

IPC分类号： H04L7/00

CPC分类号： H04L7/00

摘要： A receiving apparatus includes: a clock-data recovery circuit to generate a clock based on receive data and a setting circuit to set a gain of a filtering process to filter a phase difference between the receive data and the clock.

摘要翻译： 接收装置包括：时钟数据恢复电路，用于基于接收数据产生时钟;以及设置电路，用于设置滤波处理的增益以滤除接收数据和时钟之间的相位差。

公开(公告)号：US20080310570A1

公开(公告)日：2008-12-18

申请号：US12184075

申请日：2008-07-31

申请人： Masato TOMITA

发明人： Masato TOMITA

IPC分类号： H04L7/00

CPC分类号： H04L7/04 ,  G06F1/12 ,  H03L7/095 ,  H03L7/107 ,  H03L7/1075 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0083 ,  H04L7/033

摘要： A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

摘要翻译： 一种用于防止CDR电路中的缺陷妨碍连接节点之间的同步并防止连接故障的方法和装置。 CDR电路从接收的数据生成同步时钟。 当从接收到接收到的数据的接收开始的第一预定时间过去时，连接失败处理器执行连接失败处理，如果在连接节点之间的同步时钟不建立，则连接失败处理器执行连接失败处理。 如果当从接收到的数据的接收开始的时间比第一预定时间短的第二预定时间过去时，校正处理器校正了基于连接节点之间的同步时钟的同步的CDR电路的操作。

公开(公告)号：US20080201598A1

公开(公告)日：2008-08-21

申请号：US12034410

申请日：2008-02-20

申请人： Masato TOMITA

发明人： Masato TOMITA

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  H04L7/0004 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/04

摘要： A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

摘要翻译： 一种用于防止CDR电路中的缺陷妨碍连接节点之间的同步并防止连接故障的方法和装置。 CDR电路从接收的数据生成同步时钟。 当从接收到接收到的数据的接收开始的第一预定时间过去时，连接失败处理器执行连接失败处理，如果在连接节点之间的同步时钟不建立，则连接失败处理器执行连接失败处理。 如果当从接收到的数据的接收开始的时间比第一预定时间短的第二预定时间过去时，校正处理器校正了基于连接节点之间的同步时钟的同步的CDR电路的操作。