公开(公告)号：US06724035B2

公开(公告)日：2004-04-20

申请号：US09733031

申请日：2000-12-11

申请人： Masuoka Fujio ,  Takuji Tanigami ,  Yoshihisa Wada ,  Kenichi Tanaka ,  Hiroaki Shimizu

发明人： Masuoka Fujio ,  Takuji Tanigami ,  Yoshihisa Wada ,  Kenichi Tanaka ,  Hiroaki Shimizu

IPC分类号： H01L27108

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115

摘要： A process for producing a semiconductor memory device comprises the steps of: (a) forming a floating gate on a semiconductor substrate having a dielectric film; (b) forming a side wall spacer comprising an insulating film on a side wall of the floating gate; (c) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask; and (d) forming a low concentration impurity layer from one side wall to a bottom surface of the groove by an oblique ion implantation to the semiconductor substrate thus resulting, and forming a high concentration impurity layer from the other side wall to the bottom surface of the groove by in inverse oblique ion implantation.

摘要翻译： 一种制造半导体存储器件的方法，包括以下步骤：（a）在具有电介质膜的半导体衬底上形成浮置栅极; （b）在所述浮动栅极的侧壁上形成包括绝缘膜的侧壁间隔物; （c）通过使用侧壁间隔物作为掩模蚀刻半导体衬底来形成沟槽; 以及（d）通过倾斜离子注入从所述凹槽的一个侧壁到所述底表面形成低浓度杂质层，从而从所述半导体衬底的所述另一侧壁到所述底表面形成高浓度杂质层 沟槽通过反斜离子注入。

公开(公告)号：US5812453A

公开(公告)日：1998-09-22

申请号：US212828

申请日：1994-03-15

申请人： Masuoka Fujio

发明人： Masuoka Fujio

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0483 ,  H01L27/115

摘要： Memory cells are divided into a plurality of series circuit units arranged in matrix fashion and comprising some memory cells connected in series. The memory cells each consist of non-volatile transistors provided with a control gate electrode, a floating gate electrode and an erase gate electrode. Bit lines to which one end of each of the series circuit units of the plurality of series circuit units arranged in one row are connected in common. Column lines are provided in common for the series circuit units that are arranged in one column and that are respectively connected to each control gate electrode of the memory cells constituting each of the series circuit unit. A voltage by which the selected non-volatile transistor works in a saturation state is applied to the control gate electrode of the selected transistor of a series circuit unit by a column line, thereby injecting hot electrons from the semiconductor substrate into the floating gate electrode. Another voltage by which the non-selected non-volatile transistor works in a non-saturation operation is applied to the gate electrodes of the remaining non-volatile transistors of the series circuit unit. By sequentially selecting memory cells in one series circuit unit, the sequential data writing operation is performed. The sequential data reading operation is performed in a similar manner.

摘要翻译： 存储单元被分成以矩阵方式布置的多个串联电路单元，并且包括串联连接的一些存储器单元。 每个存储单元由设置有控制栅电极，浮栅电极和擦除栅电极的非易失性晶体管组成。 排列成一排的多个串联电路单元的串联电路单元的一端的共同连接的位线。 对于排列成一列的串联电路单元共同地提供列线，并且分别连接到构成串联电路单元的每一个的存储单元的每个控制栅电极。 所选择的非易失性晶体管工作在饱和状态的电压通过列线施加到串联电路单元的选定晶体管的控制栅电极，从而将热电子从半导体衬底注入到浮置栅电极中。 未选择的非易失性晶体管工作在非饱和操作中的另一电压被施加到串联电路单元的剩余非易失性晶体管的栅电极。 通过依次选择一个串联电路单元中的存储单元，执行顺序数据写入操作。 以类似的方式执行顺序数据读取操作。