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公开(公告)号：US06794902B2
公开(公告)日：2004-09-21
申请号：US10172574
申请日：2002-06-14
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/01728
摘要： Methods and systems for improving a logic circuit are described. By using a voltage reducer for connecting a power-supply to a virtual ground, the voltage reducer reduces the voltage supplied by the power-supply to the virtual ground during one phase of the clock, thereby increasing the speed and efficiency of the logic circuit.
摘要翻译： 描述了用于改进逻辑电路的方法和系统。 通过使用用于将电源连接到虚拟接地的电压减小器，降压器在时钟的一个相位期间将由电源供给的电压降低到虚拟接地，从而提高逻辑电路的速度和效率。
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2.发明授权Superscalar processor having content addressable memory structures for determining dependencies 有权超标量处理器具有用于确定依赖性的内容可寻址存储器结构公开(公告)号：US06862676B1
公开(公告)日：2005-03-01
申请号：US09761494
申请日：2001-01-16
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.
摘要翻译： 呈现具有发送第一和第二输出信号的内容可寻址存储器结构的超标量处理器。 超标量处理器对指令集执行无序处理。 从第一输出信号，可以确定指令集当前获取的指令与先前的飞行中指令之间的依赖关系，并用于为所有飞行中的指令生成依赖矩阵。 从第二输出信号可以确定一旦取消了相关性就执行指令所需的数据的物理寄存器地址。
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3.发明授权System and method for accessing a memory array which tolerates non-exclusive read select enables 有权用于访问允许非排他读取选择的存储器阵列的系统和方法使能公开(公告)号：US06594184B2
公开(公告)日：2003-07-15
申请号：US09948180
申请日：2001-09-06
IPC分类号： G11C700
摘要： A memory array includes a plurality of memory cells logically arranged in M rows and N columns, wherein N is the number of memory cells per word of digital information and M is the number of words within the array. A plurality of N data output lines are associated with each of the N columns of the array for selectively retrieving output data from a word located at a predetermined word address in the array. Each data output line is selectively shared by each of the M memory cells within its associated column. Each of the cell output lines of the M memory cells in each of the N columns are logically OR-ed together to provide the output data retrieved by each data output line associated with each of the N columns.
摘要翻译： 存储器阵列包括逻辑上排列成M行和N列的多个存储器单元，其中N是数字信息每个字的存储器单元的数量，M是阵列内的字数。 多个N个数据输出线与阵列的N列中的每一个相关联，用于从位于阵列中的预定字地址的字选择性地检索输出数据。 每个数据输出线由其相关联的列中的每个M个存储器单元选择性共享。 N列中的每一个中的M个存储器单元的单元输出行的每个单元输出行一起被逻辑或并行，以提供与每个N列相关联的每个数据输出行检索的输出数据。
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