DMAC Address Translation Miss Handling Mechanism
    1.
    发明申请
    DMAC Address Translation Miss Handling Mechanism 审中-公开
    DMAC地址翻译小姐处理机制

    公开(公告)号:US20080065855A1

    公开(公告)日:2008-03-13

    申请号:US11531293

    申请日:2006-09-13

    IPC分类号: G06F12/00 G06F13/28

    摘要: A memory management unit (MMU) performs address translation and protection using a segment table and page table model. Each DMA queue entry may include a MMU-miss dependency flag. The DMA issue mechanism uses the MMU-miss dependency flag to block the issue of commands that are known to result in a translation miss. However, the direct memory access engine does not block subsequent DMA commands from being issued until they receive a translation miss. When the MMU completes processing of a miss, the MMU sends a miss clear signal to the DMA control unit to reset all MMU-miss dependency flags. When the MMU sends a miss clear signal, the DMA control unit will reset all DMA queue entries with MMU-miss dependency flags set. DMA commands in the DMA queue that were blocked from issue by the MMU-miss dependency flag may now be selected by the DMA control unit for issue.

    摘要翻译: 存储器管理单元(MMU)使用段表和页表模型执行地址转换和保护。 每个DMA队列条目可以包括MMU-miss依赖标志。 DMA问题机制使用MMU-miss依赖标志来阻止已知导致翻译缺失的命令的问题。 然而,直接存储器访问引擎不会阻止随后的DMA命令被发出,直到它们接收到转换未命中。 当MMU完成未命中的处理时,MMU向DMA控制单元发送未命中清除信号,以复位所有MMU-miss依赖标志。 当MMU发送未命中清除信号时,DMA控制单元将重置所有设置了MMU-miss依赖标志的DMA队列条目。 DMA控制单元现在可以由DMA控制单元选择DMA队列中的DMA命令,由MMU-miss依赖标志阻止发布。