公开(公告)号：US07057538B1

公开(公告)日：2006-06-06

申请号：US11033371

申请日：2005-01-10

Applicant: Matthew M. D'Amore

Inventor： Matthew M. D'Amore

IPC: H03M7/12

CPC classification number: H04L27/2035

Abstract: An encoder circuit and a related method for its operation, in which digital encoding, such as differential phase-shift keyed (DPSK) encoding, is performed as a parallel operation on N bits at a time. Each encoded bit is both output in parallel with the others of the N bits and is coupled as an input to encode the immediately next bit in the input data stream. The Nth encoded bit is fed back to the first encoder stage for use in encoding the (N+1)th bit in the input stream. The encoder typically includes a serial-to-parallel converter at the encoder inputs, and a parallel-to-serial converter at the encoder outputs.

Abstract translation: 用于其操作的编码器电路及其相关方法，其中进行诸如差分相移键控（DPSK）编码的数字编码作为N位的并行操作。 每个编码的位都与N位中的其他位并行地输出，并且作为输入耦合以对输入数据流中的紧邻位进行编码。 第N / O编码比特被反馈到第一编码器级，用于对输入流中的第（N + 1）个第比特进行编码。 编码器通常包括编码器输入处的串并转换器，以及编码器输出处的并行到串行转换器。