PROVIDING QUALITY OF SERVICE VIA THREAD PRIORITY IN A HYPER-THREADED MICROPROCESSOR
    1.
    发明申请
    PROVIDING QUALITY OF SERVICE VIA THREAD PRIORITY IN A HYPER-THREADED MICROPROCESSOR 有权
    在超级螺旋式微处理器中通过螺纹优先提供的服务质量

    公开(公告)号:US20090049446A1

    公开(公告)日:2009-02-19

    申请号:US11838458

    申请日:2007-08-14

    IPC分类号: G06F9/46

    摘要: A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. In a reservation station, mask elements are set to provide access for higher priority processing elements to more reservation entries. In a pipeline, bias logic provides a ratio of preference for selection of a high priority processing

    摘要翻译: 这里描述了一种基于优先级在多处理元件环境中提供服务质量的方法和装置。 诸如保留站和流水线等资源的消耗偏向较高优先级的处理要素。 在保留站中,设置掩码元素以提供对较高优先级处理元素的访问以获得更多的预留条目。 在流水线中,偏置逻辑提供用于选择高优先级处理的偏好比率

    Providing quality of service via thread priority in a hyper-threaded microprocessor
    2.
    发明授权
    Providing quality of service via thread priority in a hyper-threaded microprocessor 有权
    在超线程微处理器中通过线程优先级提供服务质量

    公开(公告)号:US08095932B2

    公开(公告)日:2012-01-10

    申请号:US11838458

    申请日:2007-08-14

    IPC分类号: G06F9/46

    摘要: A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. In a reservation station, mask elements are set to provide access for higher priority processing elements to more reservation entries. In a pipeline, bias logic provides a ratio of preference for selection of a high priority processing element for further processing in the pipeline.

    摘要翻译: 这里描述了一种基于优先级在多处理元件环境中提供服务质量的方法和装置。 诸如保留站和流水线等资源的消耗偏向较高优先级的处理要素。 在保留站中,设置掩码元素以提供对较高优先级处理元素的访问以获得更多的预留条目。 在流水线中,偏置逻辑提供了用于选择高优先级处理元件的偏好比,用于在管线中的进一步处理。

    Detecting and resolving locks in a memory unit
    7.
    发明授权
    Detecting and resolving locks in a memory unit 有权
    检测和解决内存单元中的锁

    公开(公告)号:US07590784B2

    公开(公告)日:2009-09-15

    申请号:US11513636

    申请日:2006-08-31

    IPC分类号: G06F13/00

    CPC分类号: G06F13/161 G06F9/524

    摘要: In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and second counters to execute one or more one remediation measures with respect to the senior request based on a value of at least one of the counters. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括一种具有第一计数器的装置,用于计数存储器单元中的高级请求的分配,耦合到存储器单元的处理器的计数周期的第二计数器以及耦合到第一和第二 计数器根据至少一个计数器的值对高级请求执行一个或多个修复措施。 描述和要求保护其他实施例。

    Detecting and resolving locks in a memory unit
    8.
    发明申请
    Detecting and resolving locks in a memory unit 有权
    检测和解决内存单元中的锁

    公开(公告)号:US20080059723A1

    公开(公告)日:2008-03-06

    申请号:US11513636

    申请日:2006-08-31

    IPC分类号: G06F13/00

    CPC分类号: G06F13/161 G06F9/524

    摘要: In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and second counters to execute one or more one remediation measures with respect to the senior request based on a value of at least one of the counters. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括一种具有第一计数器的装置,用于计数存储器单元中的高级请求的分配,耦合到存储器单元的处理器的计数周期的第二计数器以及耦合到第一和第二 计数器根据至少一个计数器的值对高级请求执行一个或多个修复措施。 描述和要求保护其他实施例。