公开(公告)号：US5239262A

公开(公告)日：1993-08-24

申请号：US839418

申请日：1992-02-21

申请人： Matthias Grutzner ,  Cordt W. Starke

发明人： Matthias Grutzner ,  Cordt W. Starke

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G06F11/22 ,  G06F11/27

CPC分类号： G06F11/27

摘要： An integrated circuit chip with built-in self-test for logic fault detection is described which comprises a number of combinational logic circuits and a number of shift register latches. The combinational logic circuits are coupled via the shift register latches and the shift register latches are connected to form test scan paths. Test weights are created and combined with test patterns and are then applied to the test scan paths of the integrated circuit chip. In contrast to the prior art where the test weights are taken out of a weight storage table, the invention generates the test weights with the help of a so-called "finite state machine", i.e. with a circuit which creates a finite number of test weights without storing them. Therefore, no weight storage table or the like is necessary and the whole tester can be incorporated on the chip.