公开(公告)号：US20240379838A1

公开(公告)日：2024-11-14

申请号：US18658910

申请日：2024-05-08

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed Darwish ,  Jun Zeng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: A vertical MOSFET has an N-type SiC drift layer connected to a drain electrode. An overlying Si layer creates an n-N heterojunction at the top of the SiC drift layer. A P-well layer and N+ source regions are formed in the Si layer. Trenched gates are formed in the Si layer that invert the P-well to create a conductive path between the Si source regions and the SiC drift region. JFET channel regions and gate regions are formed in the SiC layer for improving reliability of the MOSFET under reverse voltage conditions and under short circuit conditions. The SiC drift layer results in a higher breakdown voltage, lower on-resistance, and improved thermal conductivity, and the upper Si layer retains its higher channel mobility and stability and high gate drive efficiency.

公开(公告)号：US20240347585A1

公开(公告)日：2024-10-17

申请号：US18753743

申请日：2024-06-25

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed Darwish ,  Shih-Tzung Su

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/7813

Abstract: A vertical trench MOSFET is formed with deep P-shield regions below portions of each gate trench. The deep P-shield regions are effectively downward extensions of the P-body/well, and are electrically coupled to the top source electrode. The P-shield regions abut the bottom portions and lower sides of the gate trenches, so that those small portions of the gate trench do not create N-channels and do not conduct current. Accordingly, each trench comprises an active gate portion that creates an N-channel and a small non-active portion that abuts the P-shield regions. The spacing of the P-shield regions along each gate trench is selected to achieve the desired electric field spreading to protect the gate oxide from punch-through. No field plate trenches are needed to be formed in the active area of the MOSFET. The deep P-shield regions may be formed in trench areas that are deeper than the active gate trench areas.

公开(公告)号：US20240339494A1

公开(公告)日：2024-10-10

申请号：US18625100

申请日：2024-04-02

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed Darwish ,  Jun Zeng

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0611 ,  H01L29/7813 ,  H01L29/7832

Abstract: A vertical MOSFET has an N-type drift layer over an N+ substrate. A horizontal JFET layer overlies the drift layer, where the JFET layer has P-type gate regions and N-type channel regions. A first N-type layer overlies the JFET layer. A P-type well layer overlies the first N-type layer. Gate trenches are formed through the P-type well layer and into the first N-type layer. N-type source regions abut the top areas of the gate trenches, and a source electrode contacts the source regions. The JFET N-type channel regions are generally directly below the gate trenches for conducting a vertical current when the MOSFET is in an on state. The source electrode is electrically connected to the JFET P-type gate regions via a deep P-type contact region. The JFET N-type channel regions pinch off during short circuit high current conditions to limit drain current.

公开(公告)号：US09716152B2

公开(公告)日：2017-07-25

申请号：US15245172

申请日：2016-08-23

Applicant: ROHM CO., LTD. ,  MaxPower Semiconductor, Inc.

Inventor： Masaki Nagata ,  Shigenari Okada ,  Mohamed Darwish ,  Jun Zeng ,  Peter Su

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device according to the present invention includes a semiconductor layer having a trench, a first insulating film formed along an inner surface of the trench, and an upper electrode and a lower electrode embedded in the trench via the first insulating film and disposed above and below a second insulating film. An electric field relaxation portion that relaxes an electric field arising between the upper electrode and the semiconductor layer is provided between a side surface of the trench and a lower end portion of the upper electrode.