公开(公告)号：US09892226B2

公开(公告)日：2018-02-13

申请号：US15147152

申请日：2016-05-05

Applicant: MediaTek Inc.

Inventor： Chin-Hsiung Hsu ,  Chun-Chih Yang ,  Shih-Ying Liu ,  Che-Jung Lou ,  Chao-Neng Huang ,  Chi-Yuan Liu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.