公开(公告)号：US10539972B2

公开(公告)日：2020-01-21

申请号：US15853970

申请日：2017-12-26

Applicant: MEDIATEK INC.

Inventor： Chin-Hsun Chen ,  Hao-Yuan Lin ,  Chia-Hua Chou

IPC: G05F1/46 ,  G05F1/56 ,  G05F1/565 ,  G05F1/569 ,  G05F1/563 ,  G05F1/575 ,  G05F1/573 ,  G05F1/571

Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

公开(公告)号：US09886044B2

公开(公告)日：2018-02-06

申请号：US15043687

申请日：2016-02-15

Applicant: MediaTek Inc.

Inventor： Chin-Hsun Chen ,  Hao-Yuan Lin ,  Chia-Hua Chou

IPC: G05F1/46 ,  G05F1/563 ,  G05F1/56

CPC classification number: G05F1/46 ,  G05F1/56 ,  G05F1/563

Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.

公开(公告)号：US20180120874A1

公开(公告)日：2018-05-03

申请号：US15853970

申请日：2017-12-26

Applicant: MEDIATEK INC.

Inventor： Chin-Hsun Chen ,  Hao-Yuan Lin ,  Chia-Hua Chou

IPC: G05F1/46 ,  G05F1/56 ,  G05F1/563

Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.