公开(公告)号：US20190095776A1

公开(公告)日：2019-03-28

申请号：US15716761

申请日：2017-09-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Boaz Kfir ,  Noam Eilon ,  Meital Tsechanski ,  Itsik Levi

IPC: G06N3/04 ,  G06F9/30

Abstract: Computational apparatus includes an input buffer configured to hold a first array of input data and an output buffer configured to hold a second array of output data computed by the apparatus. A plurality of processing elements are each configured to compute a convolution of a respective kernel with a set of the input data that are contained within a respective window and to write a result of the convolution to a corresponding location in a respective plane of the output data. One or more data fetch units each read one or more segments of the input data from the input buffer. A shift register delivers the segments of the input data in succession to each of the processing elements in an order selected so that the respective window of each processing element slides in turn over a sequence of window positions covering the first array.