公开(公告)号：US20190171783A1

公开(公告)日：2019-06-06

申请号：US15829216

申请日：2017-12-01

Applicant: Mellanox Technologies Ltd.

Inventor： Alexander Martfeld

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F17/5063 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  G06F2217/06 ,  G06F2217/66

Abstract: Methods and systems for designing an integrated circuit device are described. The method includes receiving RTL descriptions of the whole device and generating lower level component descriptions. The method further includes grouping the component descriptions into blocks, analyzing the component descriptions, and identifying block internal removable components based on the analysis. The method further includes removing the removable components. Reduced design is converted into gate-level descriptions. Finally, the method includes executing high quality and high efficiency device TOP level physical implementation and generation of physical and timing constrains for block level design.

公开(公告)号：US10474778B2

公开(公告)日：2019-11-12

申请号：US15829216

申请日：2017-12-01

Applicant: Mellanox Technologies Ltd.

Inventor： Alexander Martfeld

IPC: G06F17/50

Abstract: Methods and systems for designing an integrated circuit device are described. The method includes receiving RTL descriptions of the whole device and generating lower level component descriptions. The method further includes grouping the component descriptions into blocks, analyzing the component descriptions, and identifying block internal removable components based on the analysis. The method further includes removing the removable components. Reduced design is converted into gate-level descriptions. Finally, the method includes executing high quality and high efficiency device TOP level physical implementation and generation of physical and timing constrains for block level design.