公开(公告)号：US20170104697A1

公开(公告)日：2017-04-13

申请号：US15289176

申请日：2016-10-09

Applicant: Mellanox Technologies Ltd.

Inventor： Yuval Degani ,  Yohad Tor

IPC: H04L12/861 ,  H04L12/833 ,  H04L12/935

CPC classification number: H04L49/9094

Abstract: A host connected to at least one data network has a processor having a plurality of cores, and a memory. A network interface controller is coupled to the host, and configured to transmit and receive data packets via multiple distinct physical ports. The host and the network interface controller are cooperative upon receiving a packet for storing the packet in a receive buffer of the memory, deciding in the host, responsively to a destination identifier in the packet, to forward the packet from the host to the at least one data network via another one of the physical ports, and selecting one of the cores to perform a send operation.

公开(公告)号：US10284502B2

公开(公告)日：2019-05-07

申请号：US15289176

申请日：2016-10-09

Applicant: Mellanox Technologies Ltd.

Inventor： Yuval Degani ,  Yohad Tor

IPC: H04L12/861 ,  H04L12/833 ,  H04L12/935

Abstract: A host connected to at least one data network has a processor having a plurality of cores, and a memory. A network interface controller is coupled to the host, and configured to transmit and receive data packets via multiple distinct physical ports. The host and the network interface controller are cooperative upon receiving a packet for storing the packet in a receive buffer of the memory, deciding in the host, responsively to a destination identifier in the packet, to forward the packet from the host to the at least one data network via another one of the physical ports, and selecting one of the cores to perform a send operation.