公开(公告)号：US20060259336A1

公开(公告)日：2006-11-16

申请号：US10908528

申请日：2005-05-16

申请人： Meraj Anas ,  Joshua Hicks ,  Saumil Shah ,  David Witsken ,  Joseph Barkley

发明人： Meraj Anas ,  Joshua Hicks ,  Saumil Shah ,  David Witsken ,  Joseph Barkley

IPC分类号： G06F17/50

CPC分类号： G06Q10/06 ,  G06Q10/04 ,  G06Q10/063118 ,  G06Q10/06313 ,  G06Q10/06314 ,  G06Q10/0635 ,  G06Q10/06375 ,  G06Q10/1097

摘要： Methods and systems for assessing risks associated with a project. The method includes building a tier 1 library and a tier 2 library. The tier 2 library includes project templates specific to a service/product offering or project type. Building the tier 1 and tier 2 libraries includes identifying project activities associated with a project. The building also includes identifying at least one potential failure associated with each of the project activities, associating project activities that are determined to be generic to all projects with the tier 1 library, and associating project activities that are determined not to be generic to all projects with each of the project templates in the tier 2 library. The method also includes generating a project file from the tier 1 and tier 2 libraries, and calculating a baseline risk score for each of the project activities in the project file.

摘要翻译： 评估项目风险的方法和系统。 该方法包括构建一级库和二级库。 第2层库包括专用于服务/产品或项目类型的项目模板。 构建一级和二级库包括识别与项目相关的项目活动。 该建筑还包括确定与每个项目活动相关联的至少一个潜在故障，将确定为通用的项目活动与所有项目与第1级图书馆相关联，并将确定为不通用的项目活动与所有项目相关联 每个项目模板都在第2层库中。 该方法还包括从第1层和第2层库生成项目文件，并为项目文件中的每个项目活动计算基准风险评分。

公开(公告)号：US07865856B1

公开(公告)日：2011-01-04

申请号：US12075654

申请日：2008-03-12

申请人： Andrew B. Kahng ,  Puneet Gupta ,  Saumil Shah

发明人： Andrew B. Kahng ,  Puneet Gupta ,  Saumil Shah

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G06F17/5031 ,  G06F17/5036

摘要： A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static performance analysis on a circuit represented by a transistor level netlist. The method begins with converting said transistor-level netlist to a cell-level netlist by modeling individual transistors with a cell model. Then, a static performance analyzer is used to perform a static performance analysis of said cell-level netlist. Among performance characteristics that may be analyzed are timing (static timing analysis) and leakage power. The method described may also be used for statistical static timing and power analysis.

摘要翻译： 使用静态性能分析器的方法，该静态性能分析器接受小区级网表的输入，对由晶体管级网表表示的电路执行静态性能分析。 该方法开始于通过用单元模型建模单个晶体管来将所述晶体管级网表转换为单元级网表。 然后，使用静态性能分析器来执行所述小区级网表的静态性能分析。 可以分析的性能特征是定时（静态时序分析）和泄漏功率。 所描述的方法也可用于统计静态时序和功率分析。

公开(公告)号：US07716612B1

公开(公告)日：2010-05-11

申请号：US11602043

申请日：2006-11-20

申请人： Puneet Gupta ,  Andrew Kahng ,  Saumil Shah

发明人： Puneet Gupta ,  Andrew Kahng ,  Saumil Shah

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method and system for integrated circuit optimization to improve performance and to reduce leakage power consumption of an integrated circuit (IC). The original IC includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. The method creates an optimized standard-cell library from a standard-cell library. The standard-cell library includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. Further, an optimized IC is generated by using the optimized standard-cell library from the original IC. The optimized IC has an improved performance and reduced leakage power characteristics, as compared to the original IC.

摘要翻译： 一种用于集成电路优化以提高性能并减少集成电路（IC）的泄漏功耗的方法和系统。 原始IC包括多个标称单元，并且每个标称单元包括多个晶体管。 该方法从标准单元库创建一个优化的标准单元库。 标准单元库包括多个标称单元，并且每个标称单元包括多个晶体管。 此外，通过使用来自原始IC的优化的标准单元库生成优化的IC。 与原始IC相比，优化的IC具有改进的性能和降低的漏电功率特性。