公开(公告)号：US20110066825A1

公开(公告)日：2011-03-17

申请号：US12949690

申请日：2010-11-18

申请人： Michael David MAY

发明人： Michael David MAY

IPC分类号： G06F15/80 ,  G06F9/02

CPC分类号： G06F15/16

摘要： Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.

摘要翻译： 节点阵列中的每个拥有者节点具有相应的本地节点地址，并且每个本地节点地址包括从大多数到最小有效的具有寻址意义的顺序的多个分量。 每个节点包括：映射装置，被配置为将本地节点地址的每个组件映射到相应的路由方向;以及交换机，被配置为接收具有标识目的地节点的目的地节点地址的消息。 交换机包括：用于将本地节点地址与目的地节点地址进行比较以识别最重要的非匹配分量的装置; 以及在映射到最重要的不匹配组件的方向上，在本地节点地址与目的地节点地址不匹配的情况下，将消息路由到另一节点的装置。

公开(公告)号：US20080301409A1

公开(公告)日：2008-12-04

申请号：US11755119

申请日：2007-05-30

申请人： Michael David MAY

发明人： Michael David MAY

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/3867

摘要： The invention provides a processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of those instructions defining a memory access operation. The processor comprises: a plurality of instruction buffers, each for holding at least one instruction of a thread associated with that buffer; an instruction issue stage for issuing instructions from the instruction buffers; and a memory access stage connected to a memory and arranged to receive instructions issued by the instruction issue stage. The memory access stage comprises: detecting logic adapted to detect whether a memory access operation is defined in each issued instruction; and instruction fetch logic adapted to instigate an instruction fetch to fetch an instruction of a thread when no memory access operation is detected.

摘要翻译： 本发明提供了一种用于执行线程的处理器，每个线程包括指令序列，所述指令定义操作，以及定义存储器访问操作的那些指令中的至少一些指令。 处理器包括：多个指令缓冲器，每个指令缓冲器用于保持与该缓冲器相关联的线程的至少一个指令; 用于从指令缓冲器发出指令的指令发布阶段; 以及连接到存储器并被布置成接收由指令发布阶段发出的指令的存储器访问级。 存储器访问级包括：检测逻辑，用于检测在每个发出的指令中是否定义存储器存取操作; 以及指令提取逻辑，其适于在没有检测到存储器访问操作时发起指令提取以获取线程的指令。