公开(公告)号：US09396159B2

公开(公告)日：2016-07-19

申请号：US11860914

申请日：2007-09-25

申请人： Michael K. Wong ,  Rabin A. Sugumar ,  Stephen E. Phillips ,  Hugh Kurth ,  Suraj Sudhir ,  Jochen Behrens

发明人： Michael K. Wong ,  Rabin A. Sugumar ,  Stephen E. Phillips ,  Hugh Kurth ,  Suraj Sudhir ,  Jochen Behrens

IPC分类号： H04L12/28 ,  G06F15/173

CPC分类号： G06F15/17356

摘要： A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.

摘要翻译： 服务器互连系统包括可操作以发送和接收消息的第一服务器节点和可操作以发送和接收消息的第二服务器节点。 该系统还包括与第一服务器节点通信的第一接口单元和与第二服务器节点通信的第二接口单元。 第一接口单元具有第一组消息发送寄存器和第一组消息接收寄存器。 类似地，第二接口单元具有第二组消息发送寄存器和第二组消息接收寄存器。 服务器互连系统还包括通信交换机，当第一或第二寄存器中的任一个指示有效消息准备好发送时，该通信交换机接收并路由来自第一或第二服务器节点的消息。 还提供了由服务器互连系统实现的方法。

公开(公告)号：US20090080439A1

公开(公告)日：2009-03-26

申请号：US11860914

申请日：2007-09-25

申请人： Michael K. Wong ,  Rabin A. Sugumar ,  Stephen E. Phillips ,  Hugh Kurth ,  Suraj Sudhir ,  Jochen Behrens

发明人： Michael K. Wong ,  Rabin A. Sugumar ,  Stephen E. Phillips ,  Hugh Kurth ,  Suraj Sudhir ,  Jochen Behrens

IPC分类号： H04L12/56

CPC分类号： G06F15/17356

摘要： A server interconnect system includes a first server node operable to send and receive messages and a second server nodes operable to send and receive messages. The system further comprises a first interface unit in communication with the first server node and a second interface unit in communication with the second server node. The first interface unit has a first set of message send registers and a first set of message receive registers. Similarly, the second interface unit has a second set of message send registers and a second set of message receive registers. The server interconnect system also includes a communication switch that receives and routes a message from the first or second server nodes when either of the first or second registers indicates that a valid message is ready to be sent. A method implemented by the server interconnect system is also provided.

摘要翻译： 服务器互连系统包括可操作以发送和接收消息的第一服务器节点和可操作以发送和接收消息的第二服务器节点。 该系统还包括与第一服务器节点通信的第一接口单元和与第二服务器节点通信的第二接口单元。 第一接口单元具有第一组消息发送寄存器和第一组消息接收寄存器。 类似地，第二接口单元具有第二组消息发送寄存器和第二组消息接收寄存器。 服务器互连系统还包括通信交换机，当第一或第二寄存器中的任一个指示有效消息准备好发送时，该通信交换机接收并路由来自第一或第二服务器节点的消息。 还提供了由服务器互连系统实现的方法。

公开(公告)号：US20090083392A1

公开(公告)日：2009-03-26

申请号：US11860934

申请日：2007-09-25

申请人： Michael K. Wong ,  Rabin A. Sugumar ,  Stephen E. Phillips ,  Hugh Kurth ,  Suraj Sudhir ,  Jochen Behrens

发明人： Michael K. Wong ,  Rabin A. Sugumar ,  Stephen E. Phillips ,  Hugh Kurth ,  Suraj Sudhir ,  Jochen Behrens

IPC分类号： G06F15/167 ,  G06F15/16

CPC分类号： G06F13/28 ,  H04L67/1097

摘要： A server interconnect system for sending data includes a first server node and a second server node. Each server node is operable to send and receive data. The interconnect system also includes a first and second interface unit. The first interface unit is in communication with the first server node and has one or more RDMA doorbell registers. Similarly, the second interface unit is in communication with the second server node and has one or more RDMA doorbell registers. The system also includes a communication switch that is operable to receive and route data from the first or second server nodes using a RDMA read and/or an RDMA write when either of the first or second RDMA doorbell registers indicates that data is ready to be sent or received.

摘要翻译： 用于发送数据的服务器互连系统包括第一服务器节点和第二服务器节点。 每个服务器节点可操作以发送和接收数据。 互连系统还包括第一和第二接口单元。 第一接口单元与第一服务器节点通信并具有一个或多个RDMA门铃寄存器。 类似地，第二接口单元与第二服务器节点通信并具有一个或多个RDMA门铃寄存器。 该系统还包括通信交换机，当第一或第二RDMA门铃寄存器中的任何一个指示数据准备好发送时，该通信交换机可操作以使用RDMA读取和/或RDMA写入从第一或第二服务器节点接收和路由数据 或收到。

公开(公告)号：US06880028B2

公开(公告)日：2005-04-12

申请号：US10100524

申请日：2002-03-18

申请人： Hugh Kurth

发明人： Hugh Kurth

IPC分类号： G06F12/00 ,  G06F13/14

CPC分类号： G06F13/3625

摘要： A system and method are provided for dynamically determining the priority of requests for access to a resource taking into account changes in the access needs of a requesting agent over time. A requesting agent selects a priority level from a plurality of priority selections to include with a priority request to an arbiter. Work requests requiring the access to a resource may be stored in a work request queue. The priority level may be dynamic. The dynamic priority level enables the agent to sequentially increase or decrease the priority level of a priority request when threshold values representing the number of work requests in the work request queue are reached. The threshold values which cause the priority level to be increased may be higher than the threshold values which cause the priority level to be decreased to provide hysteresis. The dynamic priority level may, alternatively, enable the agent to start a timer for timing a pending priority request for a predetermined time period. The priority level of the priority request is increased if the priority request has not been granted before the timer expires.

摘要翻译： 提供了一种系统和方法，用于动态地确定访问资源的请求的优先级，同时考虑到请求代理随时间的访问需求的变化。 请求代理从多个优先级选择中选择优先权级别以优先级请求包括到仲裁器中。 需要访问资源的工作请求可以存储在工作请求队列中。 优先级可能是动态的。 当达到表示工作请求队列中的工作请求数量的阈值时，动态优先级使得代理可以顺序增加或减少优先级请求的优先级。 导致优先级增加的阈值可能高于导致优先级降低以提供滞后的阈值。 备选地，动态优先级可以使得代理能够启动定时器以在预定时间段内定时等待优先级请求。 如果优先级请求在定时器到期之前尚未被授权，则优先级请求的优先级将增加。

公开(公告)号：US07099345B2

公开(公告)日：2006-08-29

申请号：US09995356

申请日：2001-11-27

申请人： Robert A. Dickson ,  Farroukh Touserkani ,  Thomas P. Webber ,  Hugh Kurth

发明人： Robert A. Dickson ,  Farroukh Touserkani ,  Thomas P. Webber ,  Hugh Kurth

IPC分类号： H04L12/54 ,  H04L12/28

CPC分类号： H04L49/90

摘要： Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

公开(公告)号：US06820186B2

公开(公告)日：2004-11-16

申请号：US09817509

申请日：2001-03-26

申请人： Thomas P. Webber ,  Hugh Kurth ,  Robert Dickson

发明人： Thomas P. Webber ,  Hugh Kurth ,  Robert Dickson

IPC分类号： G06F1200

CPC分类号： G06F12/04

摘要： Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer.

摘要翻译： 存储器请求及其响应包括具有指示所需分组数据的第一个字节与存储器中一行数据的第一个字节之间的未对准的移位值的标签。 接收具有关联标签的数据的分组缓冲器控制器使用移位值来相应地移动所接收的数据行。 分组数据有效载荷的第一行数据相应地移位并写入分组缓冲器。 随后的数据行需要掩盖除了N等于移位值的最后N个字节的前一行数据。 移位的数据行写在上一行上，以便写入移位的接收数据行的低位字节。 然后将移位的数据行写入分组缓冲区的下一行。

公开(公告)号：US06671690B2

公开(公告)日：2003-12-30

申请号：US09832681

申请日：2001-04-10

申请人： Thomas Peter Webber ,  Hugh Kurth

发明人： Thomas Peter Webber ,  Hugh Kurth

IPC分类号： G06F1730

CPC分类号： G06F17/30958

摘要： Methods and apparatus for deleting a member in a circular singly linked list are described. Just prior to the current pointer register being updated, its contents are copied to the previous pointer register. When the consumer needs to delete a member from the list, the previous member location is known because it is saved in the previous pointer register. In this way, deletions done at the time of scanning involve only a single SRAM write access since the contents of the current pointer register is copied into the member referenced by the previous pointer register.