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1.发明授权Digital computer with cache capable of concurrently handling multiple accesses from parallel processors 失效具有能够并行处理来自并行处理器的多个访问的缓存的数字计算机
公开(公告)号：US4794521A
公开(公告)日：1988-12-27
申请号：US757859
申请日：1985-07-22
CPC分类号： G06F12/084 , G06F12/0859
摘要： A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion of pending accesses; it determines and stores for each pending access status information prescribing the steps required to complete the access and redetermines that status information as conditions change. In working on completion of current and pending accesses, the addresses of the accesses are compared to those of memory accesses in progress on the system.
摘要翻译： 一种高速缓冲存储器，其能够并行地接受并且从并行连接的多个处理器完成多于一个的高速缓存访问。 当前访问完成电路由当前访问完成电路来处理对高速缓存的当前访问，该电路确定当前访问是否能够立即完成，并且如果能够执行，则立即完成访问，或者如果不能够将该访问传送到等待访问完成电路。 后者的电路工作在完成未决访问; 它确定并存储规定完成访问所需步骤的每个未决访问状态信息，并根据条件改变重新确定该状态信息。 在完成当前和未完成的访问时，将访问地址与正在进行的存储器访问的地址进行比较。
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2.发明授权Fixed point and floating point computation units using commonly shared control fields 失效使用常用共享控制字段的固定点和浮点运算单元
公开(公告)号：US4476537A
公开(公告)日：1984-10-09
申请号：US272777
申请日：1981-06-11
申请人： Jonathan S. Blau , James B. Stein
发明人： Jonathan S. Blau , James B. Stein
CPC分类号： G06F9/226 , G06F9/30014 , G06F9/30185 , G06F9/3885
摘要： A data processing system using separate fixed point and floating point computation units and a single control store means for controlling the operations of both units, the units being responsive to commonly shared control fields of the microinstructions supplied from the control store means during their respective operations. The floating point unit can provide single or double precision results, an additional control field of the microinstructions identifying which result is required.
摘要翻译： 一种使用单独的固定点和浮点计算单元的数据处理系统和用于控制两个单元的操作的单个控制存储装置，所述单元响应于在各自操作期间从控制存储装置提供的微指令的共同共享控制字段。 浮点单元可以提供单精度或双精度结果，微指令的附加控制字段标识需要哪个结果。
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公开(公告)号：US4405992A
公开(公告)日：1983-09-20
申请号：US256772
申请日：1981-04-23
申请人： Jonathan S. Blau , Josh Rosen
发明人： Jonathan S. Blau , Josh Rosen
CPC分类号： G06F7/483 , G06F2207/3896 , G06F2207/5352 , G06F7/4873 , G06F7/4991 , G06F7/49947 , G06F7/49994
摘要： A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.
摘要翻译： 一种使用独特程序处理各种算术运算的数据处理系统。 因此，在浮点算术尾数计算中，系统使用用于将圆比特插入到浮点结果的适当位中的新技术，其中使用先行进位比特发生器级用于减少总尾数计算时间。 此外，该系统利用独特的逻辑，其与浮点指数计算逻辑并行操作，以有效地预测最终指数结果中是否存在溢出或下溢条件，并且通知系统发生了哪些这样的条件。 此外，该系统利用简化的技术来计算乘法和除法计算所需的扩展位，其中可编程阵列逻辑单元和四位加法器单元组合用于这些目的。
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4.发明授权Floating point computation unit having means for rounding the floating point computation result 失效浮点计算单元具有使浮点计算结果舍入的装置
公开(公告)号：US4468748A
公开(公告)日：1984-08-28
申请号：US272541
申请日：1981-06-11
CPC分类号： G06F9/226 , G06F9/30014 , G06F9/30185 , G06F9/3885
摘要： A floating point computation unit for use in a data processing system in which the mantissa processing means provides an overall computation result a portion of which represents the desired mantissa result. A carry-in bit is added to the least significant bit of the overall result and is propagated through the mantissa processing means so that it can be added to the least significant bit of the desired mantissa result to provide a rounding of such desired result.
摘要翻译： 一种在数据处理系统中使用的浮点计算单元，其中尾数处理装置提供其一部分表示所需尾数结果的总计算结果。 一个进位位被添加到整个结果的最低有效位，并且通过尾数处理装置传播，使得它可以被添加到期望的尾数结果的最低有效位以提供这种期望结果的舍入。
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5.发明授权Arithmetic unit for use in a data processing system for computing exponent results and detecting overflow and underflow conditions thereof 失效用于数据处理系统的算术单元，用于计算指数结果并检测其溢出和下溢条件
公开(公告)号：US4429370A
公开(公告)日：1984-01-31
申请号：US256923
申请日：1981-04-23
申请人： Jonathan S. Blau , Josh Rosen
发明人： Jonathan S. Blau , Josh Rosen
CPC分类号： G06F7/483 , G06F2207/3896 , G06F2207/5352 , G06F7/4873 , G06F7/4991 , G06F7/49947 , G06F7/49994
摘要： A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.
摘要翻译： 一种使用独特程序处理各种算术运算的数据处理系统。 因此，在浮点算术尾数计算中，系统使用用于将圆比特插入到浮点结果的适当位中的新技术，其中使用先行进位比特发生器级用于减少总尾数计算时间。 此外，该系统利用独特的逻辑，其与浮点指数计算逻辑并行操作，以有效地预测最终指数结果中是否存在溢出或下溢条件，并且通知系统发生了哪些这样的条件。 此外，该系统利用简化的技术来计算乘法和除法计算所需的扩展位，其中可编程阵列逻辑单元和四位加法器单元组合起来用于这些目的。
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