公开(公告)号：US20130187946A1

公开(公告)日：2013-07-25

申请号：US13354627

申请日：2012-01-20

申请人： Michael Pan ,  Zehao Chang ,  John Pan

发明人： Michael Pan ,  Zehao Chang ,  John Pan

IPC分类号： G09G5/00

CPC分类号： G09G5/36 ,  G06F19/00 ,  G06F19/321 ,  G09G2340/04 ,  G09G2340/0407 ,  G09G2370/022 ,  G09G2380/08

摘要： A system and method for image data management. A tiled representation of a data set is accessed. The tiled representation includes a plurality of high-resolution tiles and a plurality of reduced-resolution tiles. A request to access said data set from a computing device is received. An image display window is determined based on said request from the computing device, where the image display window corresponds to a displayable image for display on the display device. At least one overlapping image to send the computing device is determined based on said image display window, where the at least one overlapping image is selected from the scaled full images, the plurality of high-resolution tiles, and the plurality of reduced resolution tiles. At least a portion of the at least one overlapping image is sent to the computing device.

摘要翻译： 一种用于图像数据管理的系统和方法。 访问数据集的平铺表示。 平铺表示包括多个高分辨率瓦片和多个降低分辨率的瓦片。 接收从计算设备访问所述数据集的请求。 基于来自计算设备的所述请求确定图像显示窗口，其中图像显示窗口对应于可显示图像以在显示设备上显示。 基于所述图像显示窗口确定发送计算设备的至少一个重叠图像，其中从缩放的完整图像，多个高分辨率瓦片和多个降低分辨率瓦片中选择至少一个重叠图像。 至少一个重叠图像的至少一部分被发送到计算设备。

公开(公告)号：US08773463B2

公开(公告)日：2014-07-08

申请号：US13354627

申请日：2012-01-20

申请人： Michael Pan ,  Zehao Chang ,  John Pan

发明人： Michael Pan ,  Zehao Chang ,  John Pan

IPC分类号： G09G5/00

CPC分类号： G09G5/36 ,  G06F19/00 ,  G06F19/321 ,  G09G2340/04 ,  G09G2340/0407 ,  G09G2370/022 ,  G09G2380/08

摘要： A system and method for image data management. A tiled representation of a data set is accessed. The tiled representation includes a plurality of high-resolution tiles and a plurality of reduced-resolution tiles. A request to access said data set from a computing device is received. An image display window is determined based on said request from the computing device, where the image display window corresponds to a displayable image for display on the display device. At least one overlapping image to send the computing device is determined based on said image display window, where the at least one overlapping image is selected from the scaled full images, the plurality of high-resolution tiles, and the plurality of reduced resolution tiles. At least a portion of the at least one overlapping image is sent to the computing device.

摘要翻译： 一种用于图像数据管理的系统和方法。 访问数据集的平铺表示。 平铺表示包括多个高分辨率瓦片和多个降低分辨率的瓦片。 接收从计算设备访问所述数据集的请求。 基于来自计算设备的所述请求确定图像显示窗口，其中图像显示窗口对应于可显示图像以在显示设备上显示。 基于所述图像显示窗口确定发送计算设备的至少一个重叠图像，其中从缩放的完整图像，多个高分辨率瓦片和多个降低分辨率瓦片中选择至少一个重叠图像。 至少一个重叠图像的至少一部分被发送到计算设备。

公开(公告)号：US4109315A

公开(公告)日：1978-08-22

申请号：US718741

申请日：1976-08-30

申请人： Michael Pan

发明人： Michael Pan

IPC分类号： G06F15/02 ,  G06F7/38 ,  G04B19/30

CPC分类号： G06F15/0225

摘要： A wristwatch calculator is provided with a keyboard for the entry of information into and control of operations of the apparatus. The keyboard comprises an array of switches connected in an X-Y matrix that is scanned by row and column to find and identify a key that has been depressed. The scanner is operated only when calculator circuitry in the apparatus is in a sleep or inactive mode in order to save battery power.

公开(公告)号：US20060114063A1

公开(公告)日：2006-06-01

申请号：US11000622

申请日：2004-11-30

申请人： Michael Pan

发明人： Michael Pan

IPC分类号： H03F3/04

CPC分类号： H03F3/189 ,  H03F1/30

摘要： In an RF communication system, aspects of constant or proportional to absolute temperature biasing for minimizing transmitter output power variation may comprise configuring at least one current source to provide a temperature dependent current, where the current may be constant with temperature or vary proportionally to absolute temperature. A control voltage that may be generated by an operational amplifier may be fed back to control the current source. An input reference voltage may also be generated for the operational amplifier by utilizing PN junction characteristics of at least one bipolar junction transistor. Resistance may be adjusted to allow operation of the current source at a plurality of different supply voltages, including the different supply voltages that may be less than 1.2 volts, for example. Additionally, adjusting the resistance may also allow the current to be constant with temperature or vary with temperature.

公开(公告)号：US5491428A

公开(公告)日：1996-02-13

申请号：US170052

申请日：1993-12-20

申请人： Michael Pan

发明人： Michael Pan

IPC分类号： H03K3/356 ,  H03K19/017

CPC分类号： H03K3/356165 ,  H03K19/01735

摘要： A bus line is divided into at least first and second bus segments that are coupled together via a precharge buffer, each segment seeing less effective RC than if segmentation were not present. The precharge buffer provides first and second output buffer lines (or segments) that are monitored and cross-coupled through the buffer such that each line is pulled-up or pulled-down substantially simultaneously to keep equivalent states in each. Feedback provided by the cross-coupling further hastens the process of bus pull down. Still further acceleration of the pulldown process can result by sensing bus pulldown at trip point that is higher than a conventional logic level trip point. Segmenting the bus and coupling the segments with a precharge buffer results in less equivalent RC being presented to each bus segment. Thus, effective shunt capacitance is reduced, allowing use of downsized transistors coupled to the output buffer lines to pull down the bus segments. This saves integrated circuit chip area, reduces pulldown surge current and ground bounce. Further, the decreased load capacitance achieved by using smaller pulldown load devices reduces capacitive bus loading, and thus contributes to a more rapid change of bus state. Alternatively, for a given pulldown current, the present invention permits a segmented bus to be pulled down more rapidly than a conventional non-segmented bus configuration.

摘要翻译： 总线被分成至少第一和第二总线段，其经由预充电缓冲器耦合在一起，每个段看起来比不存在分段时效果更差。 预充电缓冲器提供通过缓冲器监测和交叉耦合的第一和第二输出缓冲线（或段），使得每条线基本上同时上拉或下拉以保持每个线路中的等效状态。 交叉耦合提供的反馈进一步加速了总线下拉的过程。 通过在比常规逻辑电平跳变点高的跳变点处检测总线下拉可能导致下拉过程的进一步加速。 将总线分段并将段与预充电缓冲器耦合导致较少的等效RC呈现给每个总线段。 因此，减小了有效的并联电容，允许使用耦合到输出缓冲线的小型晶体管来下拉总线段。 这样可以节省集成电路芯片面积，减少下拉浪涌电流和地面反弹。 此外，通过使用较小的下拉负载装置实现的减小的负载电容降低了容性总线负载，并且因此有助于总线状态的更快速的改变。 或者，对于给定的下拉电流，本发明允许分段总线比常规非分段总线配置更快地被下拉。

公开(公告)号：US20060116082A1

公开(公告)日：2006-06-01

申请号：US11000599

申请日：2004-11-30

申请人： Michael Pan

发明人： Michael Pan

IPC分类号： H04B1/00

CPC分类号： H04B1/036

摘要： Aspects of compensating for transmitter output power may comprise sampling an on-chip transmitter circuit temperature at various time instants and determining a feedback temperature compensation value. At least one digital-to-analog converter may be adjusted by utilizing the feedback temperature compensation value, which may correspond to the sampled temperature. The digital-to-analog converter may be an I-component digital-to-analog converter and/or a Q-component digital-to-analog converter. At least a portion of the on-chip transmitter circuit may be characterized to determine power output dependence of the on-chip transmitter circuit on temperature variation of the on-chip transmitter circuit. Based on this characterization, a feedback temperature compensation value that may correspond to the sampled temperature may be used to adjust the digital-to-analog converter. The feedback temperature compensation value may be, for example, from a lookup table or an algorithm.

公开(公告)号：US06959222B1

公开(公告)日：2005-10-25

申请号：US09548849

申请日：2000-04-13

申请人： Kent Vuong ,  Michael Pan ,  Ernest Seagraves

发明人： Kent Vuong ,  Michael Pan ,  Ernest Seagraves

IPC分类号： G06F17/00 ,  G06F17/14

CPC分类号： G06F17/142

摘要： An engine for processing functions used in audio algorithms. The engine runs in parallel with a digital signal processor (DSP) in an audio chip to increase performance for that chip. Functions performed by the engine include biquad filtering and inverse discrete cosine transform (IDCT) including pre-multiplication, inverse Fast Fourier transform (IFFT), and post-multiplication, which would otherwise be performed by the DSP. The DSP is therefore free to perform other functions demanded by the chip. Resources in the engine are processed in a pipeline structure and are thus highly utilized. Data are stored in a predefined order to increase efficiency.

摘要翻译： 用于处理音频算法中使用的功能的引擎。 引擎与音频芯片中的数字信号处理器（DSP）并行运行，以提高该芯片的性能。 由引擎执行的功能包括二进制滤波和反相离散余弦变换（IDCT），包括预乘，逆快速傅立叶变换（IFFT）和后乘法，否则将由DSP执行。 因此，DSP可以自由地执行芯片所要求的其他功能。 引擎中的资源以管道结构进行处理，因此得到高度的利用。 以预定义的顺序存储数据以提高效率。