公开(公告)号：US06948091B2

公开(公告)日：2005-09-20

申请号：US10137569

申请日：2002-05-02

申请人： Michael W. Bartels ,  Nicholas J. Wilt ,  Scott L. Gray

发明人： Michael W. Bartels ,  Nicholas J. Wilt ,  Scott L. Gray

IPC分类号： G06F11/16 ,  H04L1/22 ,  G06F11/00

CPC分类号： H04L1/22 ,  G06F11/1679

摘要： Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.

摘要翻译： 用于促使计算平台以对在计算平台上执行的软件应用是透明的方式快速恢复运行时数据存储器阵列内的瞬时多位数据故障的方法和系统。 提供了容错数字计算系统，用于在锁步架构中利用并行处理通道。 每个处理通道包括错误检测器，其被配置为检测每个处理通道的存储器阵列中的多位数据错误。 在检测到多位数据故障时，产生中断，其中控制逻辑软件响应中断并校正每个处理通道的存储器阵列中的数据错误。

公开(公告)号：US20090164867A1

公开(公告)日：2009-06-25

申请号：US11963379

申请日：2007-12-21

申请人： Scott L. Gray

发明人： Scott L. Gray

IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/29

CPC分类号： H03M13/13 ,  G06F11/1012

摘要： Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.

摘要翻译： 公开了用于使用具有相等数量的校验位并且具有校验位和数据位交错的数据位的数量可被4整除的数字位的检测和校正存储器错误的方法和系统。 在执行存储器写入指令时，处理器可以在将代码字写入存储器单元之前产生检查位的校验位产生器发送存储器字。 当来自处理器的信号被请求存储器读取时，存储器单元可以将存储的代码字发送到校正子位发生器以产生校正子向量。 然后可以将校正子向量发送到校正位发生器和不可校正误差检测器。 这些单元可以分别向处理器发送校正的位和不可校正的误差信号。

公开(公告)号：US5909541A

公开(公告)日：1999-06-01

申请号：US668309

申请日：1996-06-26

申请人： Neil L. Sampson ,  Scott L. Gray ,  Gary Walker

发明人： Neil L. Sampson ,  Scott L. Gray ,  Gary Walker

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F11/08

CPC分类号： G06F11/1044 ,  G06F11/1633

摘要： A digital computing system includes a first and second processor clocked for locked step operation. A shared memory stores a linear block codeword across a plurality of byte-wide memory devices. The codeword includes a first dataword and a second dataword. Each of the first and second datawords includes an equal plurality of databits and each includes an equal plurality of checkbits associated therewith. First error detection and correction logic connected to the first processor receives the first dataword and checkbits associated therewith of the codeword addressed by the first processor and a second dataword and checkbits associated therewith of the codeword addressed by the second processor. First error detection and correction logic detects and/or corrects errors in the codeword. Second error detection and correction logic connected to the second processor receives the second dataword and checkbits associated therewith of the codeword addressed by the second processor and the first dataword and checkbits associated therewith of the codeword addressed by the first processor. The second error detection and correction logic detects and/or corrects errors in the codeword.

摘要翻译： 数字计算系统包括用于锁定步骤操作的计时器的第一和第二处理器。 共享存储器存储跨多个字节宽的存储器件的线性块码字。 码字包括第一数据字和第二数据字。 第一和第二数据字中的每一个包括相等的多个数据位，并且每个都包括与其相关联的相等的多个校验位。 连接到第一处理器的第一错误检测和校正逻辑接收由第一处理器寻址的与第一数据字和与之对应的码字的校验位，以及第二数据字和由第二处理器寻址的码字相关联的校验码。 第一错误检测和校正逻辑检测和/或校正码字中的错误。 连接到第二处理器的第二错误检测和校正逻辑接收与由第二处理器寻址的码字相关联的第二数据字和与之对应的第一数据字以及由第一数据字与由第一处理器寻址的码字相关联的校验码。 第二错误检测和校正逻辑检测和/或校正码字中的错误。

公开(公告)号：US08103934B2

公开(公告)日：2012-01-24

申请号：US11963379

申请日：2007-12-21

申请人： Scott L. Gray

发明人： Scott L. Gray

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： H03M13/13 ,  G06F11/1012

摘要： Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.

摘要翻译： 公开了用于使用具有相等数量的校验位并且具有校验位和数据位交错的数据位的数量可被4整除的数字位的检测和校正存储器错误的方法和系统。 在执行存储器写入指令时，处理器可以在将代码字写入存储器单元之前产生检查位的校验位产生器发送存储器字。 当来自处理器的信号被请求存储器读取时，存储器单元可以将存储的代码字发送到校正子位发生器以产生校正子向量。 然后可以将校正子向量发送到校正位发生器和不可校正误差检测器。 这些单元可以分别向处理器发送校正的位和不可校正的误差信号。

公开(公告)号：US5086429A

公开(公告)日：1992-02-04

申请号：US506714

申请日：1990-04-10

申请人： Scott L. Gray ,  Steven R. Thompson

发明人： Scott L. Gray ,  Steven R. Thompson

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20

CPC分类号： G06F11/1645 ,  G06F11/2038 ,  G06F11/1044 ,  G06F11/2043

摘要： A highly reliable data processing system using the pair-spare architecture obviates the need for separate memory arrays for each processor. A single memory is shared between each pair of processors wherein a linear block code error detection scheme is implemented with each shared memory, wherein the effect of random memory faults is sufficiently detected such that the inherent fault tolerance of a pair-spare architecture is not compromised.

摘要翻译： 使用配对备用架构的高度可靠的数据处理系统消除了对于每个处理器的单独存储器阵列的需要。 单个存储器在每对处理器之间共享，其中每个共享存储器实现线性块代码错误检测方案，其中充分检测随机存储器故障的影响，使得对 - 备用架构的固有容错不受影响 。