公开(公告)号：US06484291B1

公开(公告)日：2002-11-19

申请号：US09559324

申请日：2000-04-27

申请人： Michihiro Amiya ,  Akihiro Nakamura

发明人： Michihiro Amiya ,  Akihiro Nakamura

IPC分类号： H01L2182

CPC分类号： H01L27/118 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H01L2924/00

摘要： A library used for manufacturing a semiconductor IC and a method of manufacturing the semiconductor IC. The library includes structures designed with a predetermined design rule. The library has a main part including one or more circuit elements, and a connecting terminal connected to the main part. The connecting terminal has a width less than a minimum space between the conductive patterns of the predetermined design rule. The library further includes a head portion connected to the connecting terminal at an end thereof. A width of the head portion is greater than the minimum space between the conductive patterns of the predetermined design rule.

摘要翻译： 用于制造半导体IC的库和制造半导体IC的方法。 图书馆包括按预定设计规则设计的结构。 图书馆的主要部分包括一个或多个电路元件，以及连接到主要部分的连接端子。 连接端子具有小于预定设计规则的导电图案之间的最小空间的宽度。 图书馆还包括在其一端连接到连接端子的头部。 头部的宽度大于预定设计规则的导电图案之间的最小间距。

公开(公告)号：US6127208A

公开(公告)日：2000-10-03

申请号：US90255

申请日：1998-06-04

申请人： Michihiro Amiya ,  Akihiro Nakamura

发明人： Michihiro Amiya ,  Akihiro Nakamura

IPC分类号： H01L21/82 ,  H01L27/118

CPC分类号： H01L27/118 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14

摘要： A library used for manufacturing a semiconductor IC and a method of manufacturing the semiconductor IC. The library includes structures designed with a predetermined design rule. The library has a main part including one or more circuit elements, and a connecting terminal connected to the main part. The connecting terminal has a width less than a minimum space between the conductive patterns of the predetermined design rule. The library further includes a head portion connected to the connecting terminal at an end thereof. A width of the head portion is greater than the minimum space between the conductive patterns of the predetermined design rule.

摘要翻译： 用于制造半导体IC的库和制造半导体IC的方法。 图书馆包括按预定设计规则设计的结构。 图书馆的主要部分包括一个或多个电路元件，以及连接到主要部分的连接端子。 连接端子具有小于预定设计规则的导电图案之间的最小空间的宽度。 图书馆还包括在其一端连接到连接端子的头部。 头部的宽度大于预定设计规则的导电图案之间的最小间距。

公开(公告)号：US5506428A

公开(公告)日：1996-04-09

申请号：US281457

申请日：1994-07-27

申请人： Toru Inoue ,  Michihiro Amiya ,  Tadao Takahashi

发明人： Toru Inoue ,  Michihiro Amiya ,  Tadao Takahashi

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

CPC分类号： H01L27/11807 ,  H01L23/5286 ,  H01L2924/0002

摘要： A gate array LSI having functional blocks formed by interconnecting a plurality of basic cells arranged on a semiconductor substrate in matrix form and either signal conductive patterns or first power conductive patterns. According to the gate array LSI, the first power conductive patterns are disposed on the plurality of basic cells arranged in line and are divided and disposed on the basic cells so as to interpose the signal conductive pattern therebetween. It is therefore possible to improve the efficiency of wiring macrocells.

摘要翻译： 具有通过将配置在半导体基板上的多个基本单元以矩阵形式进行互连而形成的功能块的栅极阵列LSI，以及信号导通图案或第一导电图案。 根据栅极阵列LSI，第一电力导体图案设置在多个基本单元上并排布置在基本单元上，以便在其间插入信号导电图案。 因此，可以提高接线宏单元的效率。