公开(公告)号：US20220284934A1

公开(公告)日：2022-09-08

申请号：US17456819

申请日：2021-11-29

Applicant: Microchip Technology Incorporated

Inventor： Victor Nguyen

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/14

Abstract: An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may further include a first path defined by the second inverter that includes an impedance element to resist a flow of charge suitable to change the signal state. The apparatus may further include the first inverter and a third inverter selectively cross-coupled between the first node and the second node to store a received signal state represented by the complementary voltages at the first node and the second node responsive to an assertion of a write enable signal.

公开(公告)号：US11742005B2

公开(公告)日：2023-08-29

申请号：US17456819

申请日：2021-11-29

Applicant: Microchip Technology Incorporated

Inventor： Victor Nguyen

IPC: G11C11/417 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G11C11/412

CPC classification number: G11C7/1084 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  G11C11/417 ,  G11C11/4125

Abstract: An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may further include a first path defined by the second inverter that includes an impedance element to resist a flow of charge suitable to change the signal state. The apparatus may further include the first inverter and a third inverter selectively cross-coupled between the first node and the second node to store a received signal state represented by the complementary voltages at the first node and the second node responsive to an assertion of a write enable signal.