公开(公告)号：US20230055422A1

公开(公告)日：2023-02-23

申请号：US17409476

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20250037768A1

公开(公告)日：2025-01-30

申请号：US18919650

申请日：2024-10-18

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

公开(公告)号：US12159674B2

公开(公告)日：2024-12-03

申请号：US17409476

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

IPC: H10B43/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.