LOW DENSITY PARITY CHECK CIRCUIT
    1.
    发明申请
    LOW DENSITY PARITY CHECK CIRCUIT 有权
    低密度奇偶校验电路

    公开(公告)号:US20150270851A1

    公开(公告)日:2015-09-24

    申请号:US14218315

    申请日:2014-03-18

    CPC classification number: G06F11/1076 H03M13/1105 H03M13/6505

    Abstract: Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.

    Abstract translation: 这里通常讨论的是低密度奇偶校验(LDPC)电路布局。 示例性LDPC电路可以包括组合逻辑和多个存储器单元。 多个存储器单元中的每一个可以彼此电耦合并且组合逻辑,并且多个存储器单元可以位于环状配置中。

    Low density parity check circuit
    2.
    发明授权
    Low density parity check circuit 有权
    低密度奇偶校验电路

    公开(公告)号:US09411684B2

    公开(公告)日:2016-08-09

    申请号:US14218315

    申请日:2014-03-18

    CPC classification number: G06F11/1076 H03M13/1105 H03M13/6505

    Abstract: Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.

    Abstract translation: 这里通常讨论的是低密度奇偶校验(LDPC)电路布局。 示例性LDPC电路可以包括组合逻辑和多个存储器单元。 多个存储器单元中的每一个可以彼此电耦合并且组合逻辑,并且多个存储器单元可以位于环状配置中。

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