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    Selection component that is configured based on an architecture associated with memory devices
    2.
    发明授权
    Selection component that is configured based on an architecture associated with memory devices 有权

    公开(公告)号：US11347415B2

    公开(公告)日：2022-05-31

    申请号：US17135476

    申请日：2020-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Henrico L. Yahja ,  Steven Eskildsen ,  Dustin J. Carter

    IPC: G06F3/06

    Abstract: A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device. The decoder component is to decode the received signal and transmit the decoded signal to each of the set of memory devices. The decoded signal is to enable the transmission of the data between the multiplexer and the corresponding memory device via the particular output channel.

    MANAGEMENT OF ERASE SUSPEND AND RESUME OPERATIONS IN MEMORY DEVICES
    3.
    发明申请
    MANAGEMENT OF ERASE SUSPEND AND RESUME OPERATIONS IN MEMORY DEVICES 有权

    公开(公告)号：US20220121385A1

    公开(公告)日：2022-04-21

    申请号：US17562329

    申请日：2021-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Chandra M. Guda ,  Suresh Rajgopal

    IPC: G06F3/06

    Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.

    Active input/output expander of a memory sub-system
    5.
    发明授权
    Active input/output expander of a memory sub-system 有权

    公开(公告)号：US11132292B2

    公开(公告)日：2021-09-28

    申请号：US16709380

    申请日：2019-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Jeremy W. Butterfield ,  Sean E. Nerich ,  Dustin J. Carter

    IPC: G06F12/02 ,  G06F12/0831 ,  G06F9/54 ,  G06F12/0882 ,  G06F12/0868

    Abstract: A read command to read a target memory die of a memory sub-system is received from a host system via a host-side interface of an active input/output (I/O) expander. The active I/O expander identifies a page address corresponding to the target memory die and decodes the read command to send to a memory stack associated with the page address corresponding to the target memory die. Read data is received via a memory-side interface of the active I/O expander from the memory stack including the target memory die. A signal conditioning operation is performed on the read data to generate conditioned read data. The active I/O expander sends, via the host-side interface, the conditioned read data to the host system.

    SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASSOCIATED WITH MEMORY DEVICES
    6.
    发明申请
    SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASSOCIATED WITH MEMORY DEVICES 有权

    公开(公告)号：US20210117115A1

    公开(公告)日：2021-04-22

    申请号：US17135476

    申请日：2020-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Henrico L. Yahja ,  Steven Eskildsen ,  Dustin J. Carter

    IPC: G06F3/06

    Abstract: A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device. The decoder component is to decode the received signal and transmit the decoded signal to each of the set of memory devices. The decoded signal is to enable the transmission of the data between the multiplexer and the corresponding memory device via the particular output channel.

    MANAGING ATTRIBUTES OF MEMORY COMPONENTS
    7.
    发明申请
    MANAGING ATTRIBUTES OF MEMORY COMPONENTS 有权

    公开(公告)号：US20210064278A1

    公开(公告)日：2021-03-04

    申请号：US16552484

    申请日：2019-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Ali Feiz Zarrin Ghalam

    IPC: G06F3/06 ,  G06F12/0802

    Abstract: Aspects of the present disclosure provide systems and methods for managing configuration, timing, and power parameters in memory sub-systems through the allocation of an I/O expander at a position between the controller and a drive that comprises a plurality of NAND dies. In particular, a memory controller is coupled to a drive with an I/O expander, and the I/O expander is assigned a LUN address of one or more memory components of the drive. A user or administrator of the host system can generate requests to configure target features of memory components of the drive by causing the I/O expander to decouple portions of the drive to provide a logical pathway between the memory controller and one or more memory components through reference to the corresponding LUN addresses.

    Handling of host-initiated requests in memory sub-systems
    9.
    发明授权
    Handling of host-initiated requests in memory sub-systems 有权

    公开(公告)号：US11614890B2

    公开(公告)日：2023-03-28

    申请号：US16526649

    申请日：2019-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Marc S. Hamilton ,  Suresh Rajgopal

    IPC: G06F3/06

    Abstract: One or more requests are received from a host system while a media management scan is in progress on a memory component in a memory sub-system. The media management scan in progress is suspended. The request received from the host system are serviced. Once the host system is serviced, the media management scan is resumed on the memory component.

    SERIAL INTERFACE FOR AN ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM
    10.
    发明申请
    SERIAL INTERFACE FOR AN ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20230075279A1

    公开(公告)日：2023-03-09

    申请号：US17468264

    申请日：2021-09-07

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Rajgopal ,  Chulbum Kim ,  Dustin J. Carter

    IPC: G06F13/16 ,  G06F13/42 ,  G06F12/10

    Abstract: An input/output (I/O) command referencing a logical address of a memory sub-system is received by an active input/output expander (AIOE). The I/O command is received from a memory sub-system controller via the AIOE. The AIOE identifies a physical block address corresponding to the logical block address. The AIOE identifies, among a plurality of memory devices, a memory device associated with the physical block address. The AIOE converts the I/O command received via the serial interface to a parallel interface compliant I/O command. The AIOE sends the parallel interface compliant I/O command to the memory device.

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